本文详细研究了这种分离事务流水执行技术并应用该技术实现了X处理器系统总线部件。
We study the split transaction pipelining technology in detail, and apply it to the implementation of system bus component in X processor.
一种主机控制器在处理器的控制下经由总线通信系统在单独事务中传送数据。
A host controller transfers data over a bus communication system, under the control of a processor, in individual transactions.
事务窃取一直是困扰CPU与PCI总线实现协议通信的难题。
Completion stealing is a problem difficult to deal with in protocol communication between CPU and PCI bus.
所有型号有8 (2x4)M B缓存在第二级和系统总线的财经事务局1066兆赫。
All models have 8 (2x4) MB cache in the second level and system bus OF FSB 1066 MHz.
所有型号有8 (2x4)M B缓存在第二级和系统总线的财经事务局1066兆赫。
All models have 8 (2x4) MB cache in the second level and system bus OF FSB 1066 MHz.
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