本文介绍了一个专门面向网络协议处理的硬件多线程包处理微引擎NRS05的设计。

This paper proposed a packet processing engine architecture called NRS05, that promotes the efficient dynamic thread scheduling for hiding long latency operations and coping with pipeline stalls.

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对网络处理器中多微引擎并行处理的两种编程模型进行分析，讨论了如何将数据包处理任务在多个微引擎之间进行分配，从而取得较高处理性能的一般性策略问题。

This paper shows two programming models of Multi-Microengine parallel processing in Network Processor and presents a better way of assigning packet-processing tasks among microengines.

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本文首先从结构上说明了网络处理器的构成，每个模块的功能和作用，以及模块之间的通信方式，并对其中的关键部件“微引擎”进行了详细的说明。

In this paper, the structure of the network processor and the communication of the models were introduced, especially, for the detail of the key model, Microengine.

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本文首先从结构上说明了网络处理器的构成，每个模块的功能和作用，以及模块之间的通信方式，并对其中的关键部件“微引擎”进行了详细的说明。

In this paper, the structure of the network processor and the communication of the models were introduced, especially, for the detail of the key model, Microengine.

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