本文提出异步时序电路的设计方法。
A method of designing asynchronous sequential circuits is presented.
本文提出一种异步时序电路设计的符号卡诺图的新方法。
This paper presents a new method of asynchronous design is illustrated by the symbolic Karnaugh map.
本文还针对异步时序电路测试生成问题进行了有益的研究。
In this dissertation, some beneficial researches on test pattern generation for asynchronous circuits are taken.
然而，高效的产品测试技术依然是异步时序电路大规模应用的一个很大的障碍。
However, an efficient and effective production test technique is the final hurdle of the mass application of the asynchronous circuits.
在异步时序电路设计中，它将时钟方程和状态方程的求解归在统一的符号卡诺图上进行。
In design of pulsed asynchronous sequential circuits, it will solve for equations of clock and equations of state, on a symbolic Karnaugh map.
本文根据电路中采用的触发器的不同敏感沿，提出采用组合时钟的异步时序电路的设计和分析方法。
According to different sensitive transitions of flip-flops used in sequential circuits, design and analysis methods for asynchronous sequential circuits are proposed by using the combinatorial clock.
从介绍触发器广义特性方程入手，阐述了应用它分析异步时序电路的原理和方法，并举例说明了应用。
The start from introduction of the general characteristic formula of trigger, and explains the theory and methods on analyzing as-synchronized sequential circuit. Examples are also given.
从介绍触发器广义特性方程入手，阐述了应用它分析异步时序电路的原理和方法，并举例说明了应用。
The start from introduction of the general characteristic formula of trigger, and explains the theory and methods on analyzing as-synchronized sequential circuit.
对异步时序电路的分析和使用是一个比较困难的问题，所以，异步时序电路的实际应用范围远不如同步时序电路。
It is rather difficult to analyze and make use of asynchronous sequential circuits, so the application of asynchronous sequential circuits is much narrower than synchronous ones.
重点介绍了时序电路的优化、异步设计、高层次电路设计和优化技术。
The optimization and asynchronous design of sequencing circuits and high level circuit design and optimizing techniques are described in particular.
重点介绍了时序电路的优化、异步设计、高层次电路设计和优化技术。
The optimization and asynchronous design of sequencing circuits and high level circuit design and optimizing techniques are described in particular.
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