本延迟电路的电容电量能通过所述放电电路迅速释放。
The electric quantity of the capacitance in the delay circuit can be discharged rapidly through the discharge circuit.
脉冲宽度发生器404可包括例如一个或更多个延迟电路。
Pulse width generator 404 can include, for example, one or more delay circuits.
延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。
The delay circuit is used for both frequency and phase adjustments of the output clock.
每个延迟路径可具有任何合适数目的反相器或任何合适数目的其它类型延迟电路。
Each of the delay paths can have any suitable number of inverters or any suitable number of another type of delay circuit.
最后进行了交错并联功率因数校正电路的实验研究，详细讲述主电路、控制电路及延迟电路的设计过程。
The design process of the main circuit, the control circuit and the time-delay circuit are elaborated after an experimental research of interleaving PFC converters.
延迟电路26i和延迟电路26Q中的每一个以根据目标位置的深度而定的延迟量对连续波进行延迟，并输出延迟的参考信号。
Each of the delay circuits 26i and 26q delays the continuous wave by a delay amount in accordance with a depth of a target position and outputs a delayed reference signal.
从PSK调制器20输出的连续波在延迟电路26I和延迟电路26Q中被延迟，然后作为参考信号提供给接收混频器30的每个混频器。
The continuous wave output from the PSK modulator 20 is delayed in delay circuits 26I and 26Q and is then supplied, as a reference signal, to each of mixers of a receiving mixer 30.
本文简述了余度技术中的模型监控，介绍了籍助于模拟技术确定模型监控中各参数的方法，所得的参数——安全门限值和延迟电路的时间常数可作设计比较器的依据。
This paper gives an explicit description of the model monitoring in redundance technique It brings forth a method of determining parameters in model monitoring by using simulation technique.
比较器电路也许会出现偏移量，导致触发时机的提前或是延迟。
The comparator circuit may develop offsets, causing it to trigger early or late.
在包括3个或更多延迟路径的本发明实施例中，电路515传输多个选择信号给乘法器以选择适当的延迟路径。
In embodiments of the present invention that include 3 or more delay paths, circuit 515 transmits multiple select signals to the multiplexer to select the appropriate delay path.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder , which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
介绍了一种用于光电倍增管的可变延迟高压门控开关电路。
A high voltage gating switch of variable delay for photomultiplier tube has been fabricated.
本文提出了一种在输入信号上升延迟滞的比较器电路。
This paper introduces a hysteresis comparator whose output can be delayed when the input signal is in rising time.
提出一种用于测试组合电路中延迟故障的新功能故障模型，讨论该模型的功能测试生成。
This paper propose a functional fault for delay faults in combinational circuits and describe a functional test generation procedure based on this model.
讨论了数字电路的逻辑级模拟中元件传输延迟模型、元件状态值模型的建立，逻辑模拟的算法以及元件计算的方法。
Discuss the three aspets of the logical-level simulation theory of digital circuits: the construction of delay model and multi-state model, simulation algorithms, and methods of component computation.
讨论了AMLCD周边集成驱动电路中的延迟导致的输出信号的失真。
Output signal distort of the drive circuit due to rc delay in peripheral integrated AMLCD is discussed.
采用恒比定时电路以及时幅转换显著提高了对延迟时间的测量精度。
The device Adopt the constant-ratio electric circuit and time-amplitude conversion, the accuracy of delay time raised biggest.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
指定数字电路时间∶安装和占用时间和逻辑传播延迟。
Specify digital circuit timing: setup and hold times and logic propagation delays.
既而详细地介绍了数据采集、精密步进延迟等关键电路的设计实现。
And then, introduces the implementation of significant circuits, including data acquisition circuit and precision step delay circuit.
如果延迟超过预定的时间量，则过载保护电路关闭电压调节器。
If the delay exceeds a predetermined amount of time, the overload protection circuit shuts down the voltage regulator.
最后，我们提出一个利用路径延迟惯性原理，来测试系统电路连线之串音障碍的新测试方法。
Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed.
该电路包括第一滤波级、延迟元件、以及谐波滤波器。
The circuit comprises a first filtering stage; a delay element; and a harmonic filter.
该扫描路径上的延迟减少对外部缓冲器的需求，进而在集成电路扫描测试时避免保持时间违反。
The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.
针对目前国内对自计时电路设计原理方面的研究才刚刚起步的现状，采用抽象和具体相结合的对比研究方法，对握手协议和延迟假定进行了深入研究，并对研究结果进行了直观的说明。
To the actualities that domestic study of self-timed circuit design principles is just in the primary stage, a in-depth study of handshake protocol and delay assumption have been done.
本文介绍了一种只用一块NE555时基电路和少量分立元件，就能制作一个具有过压、欠压和断电延迟三种保护功能的全自动电冰箱保护器。
The author introduces the process of using NE555circuit and a few fittings to make a tutamen of automatic refrigerator with functions of over-pressure, deficient pressure, and delay.
介绍点火正时灯检测原理，主要对非延迟式点火正时灯电路的组成及原理进行分析。
The author introduces the detection principle of non-delayed ignition timing light, mainly analyzes its circuit composition and principle.
介绍点火正时灯检测原理，主要对非延迟式点火正时灯电路的组成及原理进行分析。
The author introduces the detection principle of non-delayed ignition timing light, mainly analyzes its circuit composition and principle.
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