RISC通过保证每一个指令的长度相等的方法避免了这个问题，使指令在并行结构中更容易被流水线操作。
RISC avoided this problem by keeping every instruction at the same length, making it easier for instructions to be pipelined in parallel.
本文分析了常用对称密码算法DES、3des和AES的可重构性，利用流水线、并行处理和可重构技术，提出了一种可重构体系结构。
In this paper, based on the analysis about the reconfiguration of the DES, 3des and AES, we propose a reconfigurable architecture, which combines reconfiguration technology with pipeline, par.
该处理器内存资源消耗较并行结构有所减少，运算速度较单独的SDF流水线结构有所提高。
Compared with the full parallel architecture, the memory cost of the designed processor decreases, thus the speed is higher than that of the SDF pipeline architecture.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
该设计提出了一种将常用的并行SIMD结构与流水线MISD结构相结合的新颖并行视频处理体系结构形式。
In this process, a unique parallel video processing architecture combined with SIMD and pipeline MISD is proposed. Modules within the coprocessor are designed individually.
该技术与传统流水技术的不同在于，能从复杂的循环结构中发掘流水并行。
The technique exploits pipelining from complex loop structures, which distinguishes itself from traditional pipelining techniques.
提高FFT处理速度的主要途径是采用流水线结构和并行运算。
The main approaches of improving FFT processing speed include pipeline and parellel architecture.
电路采用可变结构帧存形式，与两片TMS320C40灵活的外部接口及强大的通信能力相结合，使系统可方便地组织成SIMD、MIMD等并行处理结构及流水处理结构；
This, combined with the flexible interface and powerful communication capability of TMS320C40 , made the system be easily configured as SIMD, MIMD parallel and pipeline structures.
FPGA在分布式计算、并行处理、流水线结构上有独特的优势，自然成为设计软件无线电系统的首选技术之一。
FPGA has become the first choice for designing the software radio system because of its unique advantages in distributed computing, parallel processing and pipelining.
改进了DCT变换算法，设计了并行查找表结构的乘法器，采用了流水线优化算法来解决时间并行性问题，提高了DCT模块的运算速度。
Design an multiplication based on parallel LUT (Look up Table). The problem of time parallel is resolved with pipeline optimization algorithm, the speed of DCT is accelerated.
改进了DCT变换算法，设计了并行查找表结构的乘法器，采用了流水线优化算法来解决时间并行性问题，提高了DCT模块的运算速度。
Design an multiplication based on parallel LUT (Look up Table). The problem of time parallel is resolved with pipeline optimization algorithm, the speed of DCT is accelerated.
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