并给出了 A/D转换器并行工作的实现框图和实用电路。
The A/D converter function chart and parallel converter circuit is given.
如果你用长电缆，或驱动(例如并行DAC)几个数模转换器，对于缓冲区中的数据信号它是很好的做法。
If you are driving long cables, or are driving several DACs (parallel DAC for example), it is good practice to buffer the data signal.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
在列并行模数转换器理论的研究基础上着手实际电路的设计。
Based on all the study above, a real column parallel single-slope ADC circuit is designed.
基于CMOS图像传感器应用，针对列并行的单斜模数转换器设计了一种内在精度高、分辨率可调的斜坡发生器ip核。
An intrinsic accuracy, adjustable resolution ramp generator IP core designed for the column single-slope ADC in a CMOS image sensor is presented.
基于CMOS图像传感器应用，针对列并行的单斜模数转换器设计了一种内在精度高、分辨率可调的斜坡发生器ip核。
An intrinsic accuracy, adjustable resolution ramp generator IP core designed for the column single-slope ADC in a CMOS image sensor is presented.
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