本文通过对并行环境下非确定有限自动机和确定有限自动机的等价性和转换进行研究，详细分析了非确定有限自动机到确定有限自动机的并行转换方法及算法，并以实例给出了其间并行转化的过程。
This paper through to research the equivalence and conversion of NFA and DFA in parallel environment, labor the method of NFA convert to DFA, and give a example of the process of parallel conversion.
并给出了 A/D转换器并行工作的实现框图和实用电路。
The A/D converter function chart and parallel converter circuit is given.
GParsExecutorsDSL使得我们更容易将清单1中的程序从串行处理转换为并行处理，如清单 2 所示
The GPars Executors DSL makes it easy to transform the program in Listing 1 from serial processing to parallel processing, as shown in Listing 2
在本例中，SIBus中介用于将 CurrencyStock请求转换为两个对xMethodsStockQuote和货币转换服务的新请求，接着并行执行这两个服务。
In this example, SIBus mediations are used to transform the CurrencyStock request into two new requests for the xMethods StockQuote and currency conversion services, which then execute concurrently.
你可以并行载入图片，同时将它们转换成立体影像。
You can load images side-by-side and convert them on-the-fly to anaglyphs.
它采用二进制计数器以把被乘数由并行形式转换成脉冲序列形式。
It USES binary counters for the conversion of the multiplicand from parallel to pulse-train form.
它只是用于简化特定范围的数据选择和转换操作的表达方式，以将这些操作轻松、自动地并行化。
NET 3.0); it is intended only to simplify the expression of a specific range of data selection and transformation operations so that they can be easily and automatically parallelized.
结合基于LLR的ngram生成算法并行处理文本文档到向量的转换
Parallel text document to vector conversion using LLR based ngram generation
如果你用长电缆，或驱动(例如并行DAC)几个数模转换器，对于缓冲区中的数据信号它是很好的做法。
If you are driving long cables, or are driving several DACs (parallel DAC for example), it is good practice to buffer the data signal.
通过由改进了的自动化和过程更快地找到并修改缺陷来提高生产力(按照您所想并行动的方式进行转换)。
Increase productivity by finding and fixing defects faster through improved automation and processes (transform the way you think and act).
介绍了用FPGA实现串行stm - 1信号到并行的转换，讨论了技术难点和测试结果。
The converting of STM1 signal from serial into parallel by FPGA is introduced in this paper. The difficulty of realization and test results is discussed.
在FPGA读取视频信息后，先用位面分层技术把串行视频信息转换为并行数据再送到视频电缆上。
After video information read by FPGA, serial video information is transformed into parallel format by Bit-Plane Separation technology first, and then sent to video cable.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
通过编译将逻辑程序的子句转换成执行图表达式。执行时，只需简单的测试即可进行“与”并行求解。
A clause of logic programs is transformed into an execution graph expression through compilation With simple test at run-time, execution in AND-parallelism can be available.
并行化编译器可以把现有的串行程序自动或半自动地转换为并行程序。
Parallelizing compiler can transform serial programs to parallel programs automatically or semi automatically.
转换数据可通过串行或并行接口获得。
The conversion data is available via a serial or parallel interface.
这种水表终端采用接触式电刷将水表字轮各码位转换为电平信号，并将检测的电平信号并行输入单片机。
This kind of water meter adopts touching electric brush to convert code position of digital code wheel of water meter into voltage signal which will be input to micro-computer in parallel.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
介绍借助A/D转换板，通过微机并行口实现铁磁材料磁滞回线自动测绘的原理与方法。
The paper presents a principle and method of automatic measuring and plotting magnetic material's magnetic hysteresis loop via computer's parallel port have the aid of A/D transition adapter.
在列并行模数转换器理论的研究基础上着手实际电路的设计。
Based on all the study above, a real column parallel single-slope ADC circuit is designed.
在串并转换接收器中，并行数据在字节时钟的作用下并行输出。
In the deserializer, parallel data are clocked out by byte clock.
本研究以串行加工观和并行加工观的争议为理论背景，探讨学生译员的口译过程中语言转换的时间进程。
Within the context of the debate between the serial view and the parallel view, the present study investigates the time course of language reformulation in the process of interpreting.
本文重点讨论了方便调试的两种JT AG接口、扩展的以太网接口和利用CPLD将串行I IS 转换成并行总线的A/D接口的设计。
A discussion about two JTAG interfaces convenient to debug, extended Ethernet interface and the design of A/D interface converted from serial IIS by CPLD is carried out.
TL 16c 554能够实现把串行数据转换为并行数据，将并行数据转换为串行数据。
TL16C554 can transform the serial data to parallel data, vice versa.
基于CMOS图像传感器应用，针对列并行的单斜模数转换器设计了一种内在精度高、分辨率可调的斜坡发生器ip核。
An intrinsic accuracy, adjustable resolution ramp generator IP core designed for the column single-slope ADC in a CMOS image sensor is presented.
自动的并行加工不影响脱离源语外壳的释意翻译；过渡的有意识的并行加工才会导致语码转换，并影响翻译质量。
Automatic parallel processing doesn't hinder deverbalization in interpreting but deliberate parallel processing will lead to transcoding, which will affect, to some extent, the quality of the output.
本文给出了十进制与其它进制之间相互转换的并行算法，并对算法的性能进行了分析。
This paper gives a parallel algorithm for conversion between decimal number and other scale number. It also analyzes the performance of the algorithm.
在串行CRC编码实现中，移位寄存器主要完成将并行输人数据转换成串行输出数据的功能，是整个设计的重要组成部分。
The shift register's function is completion of parallel data input into serial data output. The design of shift register is an important part in the realization of CRC code.
本文给出了十进制与其它进制之间相互转换的并行算法，并对算法的性能进行了分析。
This paper gives a parallel algorithm for conversion between decimal number and other scale nu...
本文给出了十进制与其它进制之间相互转换的并行算法，并对算法的性能进行了分析。
This paper gives a parallel algorithm for conversion between decimal number and other scale nu...
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