变字长解码模块的核心是基于桶形移位器的并行解码结构，使用该结构的解码速度比一次一位的串行结构更快。
The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed, "first one detector"is designed to decode UVLC.
在尽量减少时钟消耗的前提下，此解码器可以解码每个变换块中变换系数的熵编码码流，并将结果按照块扫描顺序并行输出。
While minimizing the use of clock cycles, it could decode the coded stream of transform coefficients in each block and output the decoded coefficients in zigzag scanning order.
同时采用并行流水线技术，提高了解码的速度。
The parallel pipeline is also adopted to enhance the decode efficiency.
采用流水线的工作方式，在编码和解码端均有两片DSP并行来完成编码和解码。
There are both two DSPs to accomplish the encoding and decoding with pipeline technique in the encoder and decoder.
TI公司生产的C64系列芯片具有很强的并行处理能力和信号处理功能，是实现H。263编解码的理想平台。
With its strong parallel processing ability and signal processing capacity, the C64 series chips of ti corporation is an ideal platform to run H. 263 CODEC.
TI公司生产的C64系列芯片具有很强的并行处理能力和信号处理功能，是实现H。264编解码的理想平台。
With its strong parallel processing ability and signal processing capacity, the C64 series chips of ti corporation is an ideal platform to run H. 264 CODEC.
TI公司生产的C64系列芯片具有很强的并行处理能力和信号处理功能，是实现H。264编解码的理想平台。
With its strong parallel processing ability and signal processing capacity, the C64 series chips of ti corporation is an ideal platform to run H. 264 CODEC.
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