本文就浮点加速逻辑提出双向并行移位链式结构，并给出了该结构的逻辑实现方法。
It is put forward in the paper that a new structure is called floating-point accelerating logic with two-way parallel shift chain (TPSC).
移位寄存器是一种能以串行和并行方式输入信息的装置。
The shift register is a device in which information may enter sequentially or in parallel.
研究了串行输入，并行输出单向移位寄存器的功能。
The function of the single-direction shift register which is serial input and parallel output is mainly studied.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
并行数寄存于移位寄存器。
在串行CRC编码实现中，移位寄存器主要完成将并行输人数据转换成串行输出数据的功能，是整个设计的重要组成部分。
The shift register's function is completion of parallel data input into serial data output. The design of shift register is an important part in the realization of CRC code.
最后，”一丝不苟”VI使用大量移位寄存器在一个循环内反复传递数据，在多个并行循环间使用队列传递数据。
Finally, Meticulous VI makes extensive use of shift registers for passing data between loop iterations, and queues for passing data between parallel loops.
变字长解码模块的核心是基于桶形移位器的并行解码结构，使用该结构的解码速度比一次一位的串行结构更快。
The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed, "first one detector"is designed to decode UVLC.
变字长解码模块的核心是基于桶形移位器的并行解码结构，使用该结构的解码速度比一次一位的串行结构更快。
The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed, "first one detector"is designed to decode UVLC.
应用推荐