然而，已有的电路并行测试生成算法并未取得理想的结果，尤其对时序电路。
However, the existing circuit parallel test generation algorithms fail get good results, especially for sequential circuit.
本文在总结已有并行技术的基础上，提出了并行测试生成系统的一种动态层次框架，并给出了一种实现方案。
Based on existing parallel techniques, this paper proposes a dynamic hierarchical framework for parallel ATPG and gives an implementation scheme.
提出了评价测试向量集及其生成算法的系统化方法，运用该方法对现有的并行测试生成算法进行了深入分析。
A new systematic method for evaluating interconnect testing algorithms is presented. Using this method, the parallel testing algorithms proposed in the literature are analyZed in detail.
面对VLSI设计规模日益增大的挑战，除了电路并行以外，其它已有的基本并行策略都无法从根本上解决测试生成的复杂性问题。
Facing the challenge of design scale of VLSI becoming larger, except for circuit parallel, the existing basic parallel approaches cannot solve test generation complexity problems radically.
面对VLSI设计规模日益增大的挑战，除了电路并行以外，其它已有的基本并行策略都无法从根本上解决测试生成的复杂性问题。
Facing the challenge of design scale of VLSI becoming larger, except for circuit parallel, the existing basic parallel approaches cannot solve test generation complexity problems radically.
应用推荐