说明了对偶基比特并行乘法器在硬件规模上的优越性。
The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
根据平行并行乘法器，设计了适用于模乘运算的一维阵列组合乘法器。
The one-array combinative multiplication was designed on the basis of the parallel multiplication.
在此基础上，借助于对比特级并行乘法器的复杂度的分析，给出了一个优化最大距离可分码的算法。
Based on these, an algorithm to optimize MDS codes is introduced by analyzing the complexity of bit parallel multipliers.
研究了有限域元素在弱对偶基（WDB）下的表示，基于弱对偶基下的最优弱对偶基的计算方法，给出了有限域比特并行乘法器的设计；
The presentation of the finite field elements in WDB is studied. And based on the computing method for the optimum WDB, the design for the bit parallel multiplier of finite field is presented.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。
A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
对于色度插值，文中同样提出了一种并行处理结构，复用乘法器单元对每一行的参考数据处理进行2级乘法实现。
To process chroma interpolation, a parallel structure with a realization of 2-level multiplications for each row reference data is put on, that makes the reusage of the mulplicator.
改进了DCT变换算法，设计了并行查找表结构的乘法器，采用了流水线优化算法来解决时间并行性问题，提高了DCT模块的运算速度。
Design an multiplication based on parallel LUT (Look up Table). The problem of time parallel is resolved with pipeline optimization algorithm, the speed of DCT is accelerated.
将剩余数系统算术和冗余二进制表示算术相结合，提出了一种并行实现乘法器的算法，这种算法不仅具有溢出检测功能，而且具有容错能力。
An algorithm for the parallel realization of multiplier is presented in this paper by combining redundant Residue Number System (RRNS) with redundant binary represent.
将剩余数系统算术和冗余二进制表示算术相结合，提出了一种并行实现乘法器的算法，这种算法不仅具有溢出检测功能，而且具有容错能力。
An algorithm for the parallel realization of multiplier is presented in this paper by combining redundant Residue Number System (RRNS) with redundant binary represent.
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