该芯片的判决电路采用SCFL(源级耦合晶体管逻辑)的D触发器结构，根据矢量叠加原理设计，采用差动电流放大器构成可调移相器。
The decision circuit of the chip is applied with a DFF using SCFL structure and its tuned phase shifter with differential current amplifiers according to the principle of vector addition.
分析了VMOS基本差动输入级的传输特性，提出一种高线性度的跨导可调v MOS跨导运算放大电路。
The transfer characteristics of basic VMOS differential input stage are analyzed, a VMOS operational transconductance amplifier which has good linearity and tunable transconductance is presented.
差动输入级具有分别接收第一输入信号和第二输入信号的第一输入端和第二输入端以及具有第一输出端。
The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal.
偏压模块提供偏压电流至差动输入级。
The bias module provides a bias current to the differential input stage.
输出缓冲器包括差动输入级、偏压电流源、反馈模块以及输出级。
The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage.
控制电路部分由带通电路、一级放大电路、差动检测电路、解调电路、低通滤波电路等部分组成。
A control circuit comprises a band-pass circuit, a primary amplifying circuit, a differential detection circuit, a demodulator circuit, a lowpass filter circuit, etc.
控制电路部分由带通电路、一级放大电路、差动检测电路、解调电路、低通滤波电路等部分组成。
A control circuit part comprises a band-pass circuit, a primary amplifying circuit, a differential detection circuit, a demodulation circuit, a low-pass filtering circuit and the like.
有级调速机构、无机调速机构分别与传动系统中的调速齿轮组和差动轮系匹配。
The step speed regulating mechanism and the stepless speed regulating mechanism are separately matched with the speed regulating gear set and the differential gear train of the transmission system.
有级调速机构、无机调速机构分别与传动系统中的调速齿轮组和差动轮系匹配。
The step speed regulating mechanism and the stepless speed regulating mechanism are separately matched with the speed regulating gear set and the differential gear train of the transmission system.
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