文中介绍了一种小数分频频率合成器的设计方案。
In this paper, a solution to fractional frequency dividing frequency synthesizer is introduced.
该合成器采用程控时分复用小数分频锁相技术，解决了快速跳频频率合成中的诸多固难。
Some technique problems in fast frequency hopping synthesis are solved by making use of a programmable time division-fractional division PLL.
文中介绍了小数分频技术的基本原理，并分析了小数分频中小数杂散产生原因和抑制方法。
This paper introduces the basic principles of fractional technology, and analyzes the cause of fractional spurious and the method of suppression.
本文主要研究CMMB系统应用的小数分频PLL以及系统中高性能的鉴频鉴相器和电荷泵的实现。
The main aim of this work is to research the fractional-N PLL in the CMMB application and the realization of the high performance PFD and CP of the PLL.
在此基础上，介绍了小数分频器在直接数字频率合成技术和步进电机驱动速度控制中的两种常见应用。
Applications of decimal Fraction frequency divider in the area such as direct digital frequency synthesis technology and stepper motor drive speed controller a re introduced.
采用现场可编程门阵列（FPGA）基于小数分频器的原理，实现直接数字式频率合成器（DDS）。
The realization of direct digital synthesizer (DDS) by FPGA based on the principle of fraction division is introduced.
采用本文研究的API内插模型，小数分频的尾数调制寄生谱可以抑制到相位内插信号准确地匹配相位误差的程度。
Using the API model mentioned in this paper, the fractional spuriousness are reduced to the extent that the phase interpolation signal exactly matches the phase error.
采用本文研究的API内插模型，小数分频的尾数调制寄生谱可以抑制到相位内插信号准确地匹配相位误差的程度。
Using the API model mentioned in this paper, the fractional spuriousness are reduced to the extent that the phase interpolation signal exactly matches the phase error.
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