另一示例是，与LUT相关的以其他方式不需要的寄存器可被用于为用户RAM模式提供同步读地址信号。
As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
文章详细讨论了RTCC、OPTION寄存器、预定标器及同步延时单元的电路结构、工作原理及设计特点。
The paper details the RTCC, OPTION register, prescaler and sync delay circuit principle and design feature.
在各单元中包括寄存器，各寄存器与时钟脉冲同步，依次取得逻辑运算结果并加以保存。
Each cell contains a register. Each register successively acquires logic calculation results in synchronization with a clock and maintains them.
ICS1523是一种高性能可编程行同步信号发生器，它带有一个I2C串行总线接口，可以方便地对内部寄存器进行配置，能产生用户需要的同步信号。
ICS1523 is a high performance programmable line-lock clock generator with the I2C serial bus interface. User can use it to generate desired line-locked clock by programming it.
第四章在FPGA平台上实现载波同步单元电路，并给出了实现后的FPGA资源消耗、寄存器传输逻辑(rtl)原理图。
In chapter 4, the circuit of the carrier synchronization unit is implemented on FPGA, the Resistor Transistor Logic (RTL) schemes are presented.
一种图形处理单元流水线，通过传送来自第一模块的围篱指令至寻址同步寄存器对而执行同步。
A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair.
一种图形处理单元流水线，通过传送来自第一模块的围篱指令至寻址同步寄存器对而执行同步。
A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair.
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