由于寄存器传输级(rtl)行为描述可以精确地确定数字系统的操作，所以寄存器传输级综合成为当前EDA行业的主流设计方法。
Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。
The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
寄存器传输级(rtl)综合实现从rtl行为描述到门级结构描述的转换，是目前EDA设计行业的主流设计方法。
As the behavior of digital system can be fully described by the register transfer level (RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain.
集成电路设计在寄存器传输级的设计方法已经非常成熟。
集成电路设计在寄存器传输级的设计方法已经非常成熟。
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