其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。
This Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoders using traditional trace-back methods.
这样做可以充分利用EPROM中剩余部分的存储单元，省略译码器设备，减少出错几率。
In this way we can take good advantage of the storage location of the residual division in EPROM omit the facility of decoders and decrease the rate of the error.
控制单元由程序存储器ROM、指令译码器、地址生成模块、程序计算器PC 组成。
The control path contain Instructor ROM, instructor register, instructor decode unit, address creating module and Program Counter (PC)module.
由于该译码器有较高的纠错速率和规则的设计结构，使它可以方便地用于数据传输和存储过程中进行差错控制。
Since this decoder has high error-correcting speed and regular structure, it may apply to data transmission and storage to decrease error rate.
译码器是存储部件关键路径的重要组成部分，提高译码速度能有效提高寄存器文件和SRAM的读写速度。
Decoder is one of the most important components in a memory unit, and its improvement can greatly diminish the access time of both register file and SRAM.
译码器是存储部件关键路径的重要组成部分，提高译码速度能有效提高寄存器文件和SRAM的读写速度。
Decoder is one of the most important components in a memory unit, and its improvement can greatly diminish the access time of both register file and SRAM.
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