在动态存储器的设计当中，增加内联结构的种类和数量，可以使存取时间加快。
In the design of a dynamic memory, as the variety and number of interconnections are increased, the access time is improved significantly.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
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