用于存储存储器测试信息的方法和装置。
Methods and apparatus for storing memory test information are presented.
同时证明了该存储器测试方法的正确性。
本发明公开了一种基于扫描链的存储器测试装置及其使用方法。
The invention discloses a memorizer test device based on a scan chain and a use method thereof.
另外本文还比较详细的分析比较了常用的存储器测试算法，简要分析了VLSI测试生成算法。
In addition, the detailed analysis of some frequently used memory test algorithms and brief analysis of some test generation algorithms for VLSI are also included in this paper.
BIST控制器不仅可以执行传统的存储器测试算法，而且可以生成用于逻辑模块的测试向量。
The BIST controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part.
清单24测试外部存储器是否只可读。
清单23测试外部存储器是否可用。
记住整个文件在测试的开始就已被读入存储器是十分重要的。
It is important to remember that the entire text file is read into memory at the beginning of a test.
要获取GPFS已测试并支持的带有SCSI3 - PR支持的存储器列表，请参阅参考资料中的在线gpfsFAQ。
For a list of storage with SCSI3-PR support that has been tested and is supported by GPFS, see the online GPFS FAQ in Resources.
在事件存储器上的操作种类是非常受限的， 这使得持久化是可预期的也就使得测试变得容易了。
The kind of operations made on an event store is very limited, making the persistence very predictable and thus easing testing.
该方法由于没有采用存储器存储测试模板，所以可以节省一定的芯片面积。
Because this method doesn't use memory to store the test patterns, it can save certain area of the chip.
泰瑞达是引领全球逻辑、RF、模拟、电源、混合信号、存储器技术的自动测试设备供应商。
Teradyne is a leading worldwide supplier of automatic test equipment for logic, RF, analog, power, mixed-signal, and memory technologies.
公开了用于测试快闪存储器管芯的方法、系统和设备。
The present invention discloses methods, systems and devices for testing flash memory dies.
仿真结果表明，该方法操作简单、有效，故障覆盖率达到了90%，是一种很可行的存储器板测试生成方法。
The result indicates that the technology manipulates easily and is effective, the fault coverage reaches 90%, it is a feasible test generation technology.
各种类型的嵌入式存储器大量集成于数字芯片中，由于芯片端口的限制，直接测试这些存储器非常困难。
A large number of various embedded memory are integrated in digital chips, as the constraints of chip ports, direct test of these memories is very difficult.
本发明涉及一种测试方法，用以测试一组态只读存储器。
The invention relates to a test method for testing a configuration read-only memory.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
本文针对实际维护PCB板中对含存储器模块的电路系统的测试需求，从测试角度对ROM和RAM建立一种复杂器件模型。
This paper aimed at testing requirement of digital circuits contain memory chips during maintaining PCB, proposes a complex component model of ROM and RAM from testing angle.
集成电路工艺的改进使存储器的测试面临着更大的挑战。
Test of memory faces enormous challenge because of the semiconductor technology progress.
第一存储器(102)被配置用于存储用于视频测试图案的各部分之间的过渡的像素值，并被配置用于存储重复的像素值。
A first memory (102) is configured to store pixel values for transitions between portions of the video test pattern and configured to store a repeated pixel value.
如果测试结果为真，它会改变程序计数器的结果去，指向记忆存储器里的其他地方，指令序列里的其他地方，然后你会继续这个过程。
And if the test is true, it will change the value of this program counter to point to some other place in the memory, some other point in that sequence of instructions, and you'll keep processing.
测试仪器安装在水力活塞泵泵芯尾部取样器内，随泵芯投入井下进行测试，可实时检测地层液的含水率情况，利用数据存储器实时保存历史曲线，提供了全天候观测生产过程的手段。
Testing instrument was installed in sampler at heel of hydraulic pump, put into down-hole with pump, and it can examine water cut of formation fluid, save history curves in real time by data memory.
通过对CM OS存储器idd频谱图形测试过程的介绍，测试及试验数据证实CM OS存储器idd频谱图：形测试是可行的。
This paper introduced the realization procedure of IDD spectrum graphics. Test and experiment data proved that CMOS memory IDD spectrum graphics test is work.
文中详细分析了嵌入式存储器内建自测试的实现原理，并给出了存储器内建自测试的一种典型实现。
The principle of memory built-in self-test is analyzed in detail and a typical implementation of MBIST is given in the paper.
实际的仿真和测试结果表明，在人工耳蜗应用当中，恰当地结合使用这两种方法，可以使DS P中存储器的功耗降低50%以上。
Actual simulation and measured results show that, proper joint application of these two methods can reduce the power dissipation of the memory in the DSP by more than 50%.
随机存储器在电子装备中广泛使用，对其进行有效测试是电子装备自测试与生产功能测试的主要内容。
RAM is used widely in electrical equipment, so RAM testing is a key part for built-in test and functional test.
耦合到单个存储器的模式发生器操纵在并行测试方式过程中使用的并行测试矢量和在扫描测试方式过程中使用的并行和扫描测试矢量。
A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode.
涉及一种芯片的测试装置及其使用方法，尤其是一种存储器的测试装置及其使用方法。
The invention relates to a test device of a chip and a use method thereof, in particular to a test device of a memorizer and the use method thereof.
本发明提供了一种多媒体播放的快速芯片验证方法和装置，所述方法包括：从存储器中读取待测试的文件；
The invention provides a method and device for rapidly verifying a chip by multimedia player. The method comprises the following steps: reading a file to be tested from a memory;
本发明提供了一种多媒体播放的快速芯片验证方法和装置，所述方法包括：从存储器中读取待测试的文件；
The invention provides a method and device for rapidly verifying a chip by multimedia player. The method comprises the following steps: reading a file to be tested from a memory;
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