一个存储器地址是由输出到适宜的总线上的二进制数据所组成。这个总线我们称为地址总线。
A memory address consists of binary data being output on an appropriate bus which we call the address bus.
对系统的存储器结构、数据通信通道组成和系统总线结构进行了分析；讨论了算法划分、算法的多处理器映射及调度；
The memory structure, constitution of data communication channel and system bus are analyzed, and the algorithm allocating, algorithm mapping and scheduling on the multiprocessor are discussed.
端口0也是复低位地址和在利用外部程序和数据存储器的数据总线。
Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory.
对微控制器而言，PDIUSBD12看起来就像一个带8位数据总线和一个地址位（占用两个位置）的存储器件。
To a micro-controller, the PDIUSBD12 appears as a memory device 8-bit data bus and 1 address bit (occupying 2 locations).
数据存储传输模块采用PCI总线和FIFO数据存储器对大量的数据进行连续存储传输，保证数据的准确完整。
In data storage transmission modular, we adopt PCI bus line and FIFO data memory carry out succession for plenty of data to storage transmission, guarantee AE signal accurate collecting.
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
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