给出了在较低阈值下节约材料生长时间的各外延层厚度。
Appropriate thicknesses of epilayers are given with lower threshold gain and more economical material growth time.
实验结果证明IGBT的下降时间随着外延层厚度的增加而增加。
The experimental results prove that the fall time of IGBT increases when increasing the thickness of the epitaxial layer.
通过改变外延生长工艺来调节两层薄膜的折射率，可在一定波导的厚度范围内实现单模传输。
By adjusting the difference of refractive index of the double layer film, single mode operation can be realized with a certain waveguide thickness.
SOI衬底顶层硅呈现高阻状态，合适温度的退火可以明显降低SOI衬底顶层硅电阻率，也可部分减少外延高阻过渡层厚度。
The annealing at the proper temperature may decrease the resistivity of SOI substrate obviously and also improve the resistivity of epitaxial transitional layer partly.
主要是随着衬底尺寸的增长，外延层的厚度、电阻率均匀性无法满足要求。
With large size wafer, the uniformity of thickness & Resistivity was out of control line.
利用D-T模型考虑了界面位借间的相互作用，计算了外延层与材底为不同失配、不同厚度时，应变的释放。
In this paper, we calculate the strain relaxation in the epilayer with various thickness and mismatch, using D-T model.
以数值结果揭示外延层的体电阻率及厚度、活性区载流子的扩散长度、模增益和丝区宽度等参量对上述各种分布的影响。
Numerical results indicate how the various parameters such as bulk resistivity and carrier diffusion length in the active region affect the profiles.
以数值结果揭示外延层的体电阻率及厚度、活性区载流子的扩散长度、模增益和丝区宽度等参量对上述各种分布的影响。
Numerical results indicate how the various parameters such as bulk resistivity and carrier diffusion length in the active region affect the profiles.
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