可扩性也将改进，因为可以增加更多的处理器，而无需增加与处理器直接相连的内部数据通道，即总线。
Scalability would improve because more processors could be added without adding more internal data channels, or buses, connected directly to the processors.
XX节所描述的内部总线通过一组位于微处理器集成电路内的总线缓冲器与外部总线连接。
The internal processor bus described in Sec. XX is connected to the external processor bus by a set of bus buffers located on the microprocessor integrated circuit.
访问内部统一二级处理器缓存的后端总线接口逻辑。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
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