这证明了天线，无线电芯片，控制电路，和微米级的光源可以被集成在隐形眼镜镜片上，并且在眼睛上正常工作。
This verifies that antennas, radio chips, control circuitry, and micrometre-scale light sources can be integrated into a contact lens and operated on live eyes.
而且一个研究团队组建了一台拥有定制的集成电路的超级计算机，定制的集成电路极大地提高了蛋白质折叠计算的速度，允许在毫秒级的时间精度上进行仿真。
And one research team built a supercomputer with customized integrated circuits that dramatically speed protein-folding calculations, allowing simulations on the time scale of milliseconds.
本文介绍了该逻辑学和其在计算纳米级门电路的概率分布方面的应用。
This paper describes the logics and the using in computing the probability distribution of the nano-gate states.
集成电路设计在寄存器传输级的设计方法已经非常成熟。
在明确了系统级的总体规划以及设计层次的划分以后，我们从系统的最底层开始进行数字逻辑电路的设计。
After the system-level spec and the division of the design hierarchy are comfimed, we start to design the digital logic circuit from the bottom for the pixel machine .
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
本文结合教学，以单级放大电路为例，探讨了计算机在分析放大电路中的应用。
Based on the classroom teaching and the example of single - leveled amplifier circuit, the paper goes into the application of computers to analyzing amplifier circuits.
本文以两级阻容耦合放大电路实验为例，分析了干抚产生的原因，强调了在实验中应注意干扰的产生和消除。
The paper is to analyse how the interference produced in a two-step resistance capacitance coupled amplifier circuit experiment and show importance of its product and disappearance in the experiment.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
在电路设计过程中，对后级接口电路进行了最优化设计，采用VHDL描述的方式实现了低压数字延时电路模块的设计。
In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.
在版图的设计上，对输入级采用交叉耦合结构，减小由于工艺原理引起的MOS管匹配，从而减小电路的失调电压；
In layout design, the cross-couple structure is adopted in the input stage to minimize the MOSFET mismatch due to process, and consequently to lower the offset voltage in the circuits.
这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design.
在低阻电路上往往会出现毫伏级的杂散信号，大多数是由于热电效应引起的。
Spurious microvolt level signals are often present in low resistance circuits, most often as a result of thermoelectric effects.
本文在多值开关级代数理论的基础上，提出了适合于NMOS及CMOS组合电路的逻辑设计自动化算法。
On the basis of the multiple-valued switch-level algebra, this paper proposes a logic design automation algorithm for NMOS and CMOS combinational circuits.
在设计者进行系统和电路级设计时，时常会将要实现的逻辑功能或操作较为平均地分配到时序中的各个阶段，称之为逻辑平衡设计。
This paper focuses on the high performance very large scale integrated circuits design using the concept of logic balance at the first time.
输出级采用推挽式AB类结构，能有效地提高输出电压的摆幅，从而得到电路在低电源电压下的高驱动能力。
The output swing can be improved efficiently with push-pull class-AB output stage, thus high-drive capability with low power supply is obtained.
在功率输出级采用OCL互补对称功率放大电路，并对该功放电路增加电压负反馈，使得输出的正弦电压信号平滑而稳定。
At the power output, OCL complementally and symmetrical power amplifier is adapted. The output sine voltage becomes smooth and stable by adding voltage-negative-feedback to power amplifier.
随着集成电路工艺的飞速发展，人们已经可以将原先的板级系统集成在一块芯片上，系统芯片逐渐成为集成电路设计的主流发展趋势。
With the development of semiconductor process technology a system on a PCB (Printed Circuit Board) which is composed of several ICs can be integrated into a chip.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
对改进型最大功率跟踪策略进行了仿真，结果表明，该控制策略在本系统设计的前级BOOST电路中可以有效地跟踪太阳能最大功率点。
Simulation about MPPT is also carried out and its results explain that the control strategy designed for the former BOOST circuits of this system can track the max power point effectively.
串级逆变电路是在高压大功率电力电子变换器中应用较多的一种变换电路。
Cascade inverter has various applications in the high voltage and power multilevel inverter field.
在设计中还采用了共源共栅两级运放和差分动态比较器来优化电路的速度和功耗。
The cascode two -stage op -amp and differential dynamic comparator are also used to optimize the speed and power dissipation.
如果FPGA上的引脚分配与在电路板一级实现的设计不符的话，就会损坏fpga器件或电路板上的外围器件。
If the pin assignments within the FPGA do not agree with the implemented design at the board level, damage can occur to either the FPGA component or the board-level circuits.
应用该理论设计的三值全加器等电路具有简单的电路结构和正确的逻辑功能，从而证明了该理论在指导电流型CMOS电路在开关级逻辑设计中的有效性。
The circuits such as ternary full-adder, etc. designed by using this theory can have simpler circuit structures and correct logic functions. It is confirmed that this theory is efficient in...
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U. s. CALMARK provide board reinforcement products in the global electronics, industrial, military and space industry is second to none, known for its world-class board reinforcement products.
为解决探地雷达用于隧道地质超前预报时探测距离小的问题，在分析了雪崩三极管工作原理的基础上，设计了基于两级雪崩三极管串行级联的窄脉冲产生电路。
The status in quo of Impulse Ground Penetrating Radar and the general principle of Avalanche Transistor are discussed then a new method for Avalanche simulation is given in this thesis.
在电荷转换部分的灵敏电容的切换和输出放大级的增益切换电路的实现上提出了程控的方案；
Has proposed a programme-controlled scheme in the sensitivity throw-over of charge convert and gain throw-over of output amplifier;
在电荷转换部分的灵敏电容的切换和输出放大级的增益切换电路的实现上提出了程控的方案；
Has proposed a programme-controlled scheme in the sensitivity throw-over of charge convert and gain throw-over of output amplifier;
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