本文讨论的全数字锁相环包括过零检测器和环路滤波器。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
然后分析了现有视频解码系统和环路滤波器设计，并且指出了本设计的重点和难点以及解决的思路。
The commonly used techniques for video systems and loop-filtering are discussed. The author presents a solution and the key points.
针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。
A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
环路滤波器中的有源和无源器件均有噪声产生，此类噪声会叠加在输出信号上，从而恶化输出信号的相位噪声。
Noise which comes from both active and passive circuit element in loop filter will deteriorate phase noise of output signal.
本文的工作就是设计一种支持这两种标准编解码的环路滤波器硬件架构，并对其进行验证和性能分析。
This paper develops a hardware architecture of the multi-standard loop-filter that can be used for both standards in various codec systems.
本文的工作就是设计一种支持这两种标准编解码的环路滤波器硬件架构，并对其进行验证和性能分析。
This paper develops a hardware architecture of the multi-standard loop-filter that can be used for both standards in various codec systems.
应用推荐