以主流FPGA为平台设计了一个可重构处理器。
A reconfigurable processor is designed with the mainstream FPGA as its platform.
而可重构技术和DSP处理器的结合也使得单DSP处理器性能有望得到很大提升。
The combination of DSP processors and reconfigurable computing technology has the promising potential to improve the single DSP processor performance to a higher level.
本论文基于可重构计算系统提出了针对多媒体图像处理的可重构阵列协处理器模型RAC。
Based on the reconfigurable computing system, the thesis proposes RAC, a reconfigurable array coprocessor model, targeted at multimedia image applications.
介绍了高性能定点可重构DSP处理器的数据通路设计。
In this paper, the data path of a high performance reconfigurable DSP processor is introduced.
可重构密码协处理器组成与结构是指可重构密码协处理器的组成模块及其相互之间的连接网络。
The components are modules that construct the reconfigurable cipher coprocessor, and the structure is their connection network.
提出了可重构密码协处理器的概念并论述了其设计原理。
The concept and design principle of reconfigurable cipher coprocessor are proposed in this paper.
可重构计算系统是一种软硬件混合系统，通常包括作为主要控制器的微处理器，和作为硬件加速器的可重构硬件模块。
Reconfigurable system is a software-hardware mixed system. It generally contains microprocessor as the primary controller of the system and several reconfigurable hardware blocks as accelerators.
多dsp的管理与调度是多处理器并行、可重构结构体系控制器的基础。
Management and scheduling of multi-DSPs (Digital Signal Processing) is the basic elements of controller with parallel and reconfigurable architecture.
多dsp的管理与调度是多处理器并行、可重构结构体系控制器的基础。
Management and scheduling of multi-DSPs (Digital Signal Processing) is the basic elements of controller with parallel and reconfigurable architecture.
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