本文主要研究的是基于现场可编程逻辑阵列（FPGA）的数字上下变频技术的设计和实现。

This paper deals with the design and implementation of Digital Up Conversion and Digital Down Conversion based on the field-programmable gate array (FPGA).

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在恶劣电磁环境下，对现场可编程逻辑阵列（FPGA）工作稳定性影响较大的是外界杂波脉冲和毛刺信号。

This paper introduces that some measures of restraining pulse jamming and enhancing the stability of FPGA chips in bad electromagnetic circumstance.

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大规模可编程逻辑阵列（CPLD）的快速开发、在系统编程以及高速可靠的特点使得CPLD在数字系统的构建中起到越来越重要的作用。

The feature of rapidly develop, high speed and high reliability of Complex Program Logic Device(CPLD) makes CPLD playing a more and more role in the design of digital system.

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本文介绍了一种特殊的硬件实现方法，使用了管脚少、成本低、容易得到的逻辑接口器件，例如可编程逻辑阵列（PAL）、可编程逻辑电路（CPLD）或者FPGA。

The article introduces a unique hardware realization, which utilizes less-foot, low-cost and easy-to-get logistic interfaces, as PAL, CPLD or FPGA.

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本文介绍了一种特殊的硬件实现方法，使用了管脚少、成本低、容易得到的逻辑接口器件，例如可编程逻辑阵列（PAL）、可编程逻辑电路（CPLD）或者FPGA。

The article introduces a unique hardware realization, which utilizes less-foot, low-cost and easy-to-get logistic interfaces, as PAL, CPLD or FPGA.

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