针对指纹图像的采集、处理、显示，提出一种性价比好且易于实现的基于PC机、单片机和可编程逻辑器件的硬件平台。
A kind of hardware platform based on PC, MCU and FPGA is given for fingerprint collection, processing and displaying. It has a good performance and easy to be achieved.
CPLD芯片具有硬件逻辑在系统可编程功能，大大提高了系统设计的灵活性。
The adoption of CPLD chip whose hardware logic can be reprogrammed in system helps to enhance the flexibility of system.
针对检测数字图像灰度梯度的最大值法，采用SOBEL边缘检测算子对数字图像进行边缘检测，并利用硬件(大规模可编程逻辑器件CPLD)实现了数字图像的边缘提取。
The article will contrapose maximum value method based on detecting image grey grad, and take example of SOBEL operator to realize digital image fringe picking up based on hardware (CPLD).
硬件部分介绍了硬件整体结构，并对DSP及复杂可编程逻辑器件等部分的设计加以详细的介绍。
The whole structure of hardware and the designs based on DSP and CPLD are specially discussed in detail.
可编程逻辑器件具有器件规模大、工作速度快及可编程的硬件特点，非常适合用来实现DDS。
The programmable logical device has big scale, quick working speed and is programmable which is extremely suitably used to realize DDS.
硬件和软件设计者可以利用可编程逻辑开发各种DSP应用解决方案。
The hardware and software designer can use the programmable logic to develop each kind of DSP application solution.
介绍了造纸配浆工段的工艺流程、测控系统、以可编程逻辑控制器（PLC）为控制单元的系统结构和硬件设计，同时详细阐述了实现连续配浆的控制算法。
The paper introduces the process of continuous furnish preparation, its measuring and controlling systems, the structure and hardware design of the whole system where the PLC is used as control unit.
根据现有的软硬件技术条件，结合实际需要，本论文提出并详细分析了一种新的基于高密度可编程逻辑器件的高动态全数字解扩接收机系统。
On conditions of the current technology, the thesis puts forward a new high dynamic and whole digital spread spectrum receiver which is based on the high density programmable logic devices.
在硬件、软件上进行了优化设计特别是采用了大规模可编程逻辑器件ISPLSI- 1032E门阵列使该系统更简洁、稳定。
Especially, the system becomes more concise and stable by use of large scale programmable logic device ISPLSI - 1032e gate array.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
本文详细介绍了一种以单片机和可编程逻辑器件为控制核心的设计方案，并分析了该方案的优缺点，同时给出了硬件和软件设计的结构及思路。
This paper introduces a design based on chip microcomputer and CPLD, analyzes its advantage and disadvantage in detail and gives the hardware-software design frame and thought.
该设计采用可编程逻辑器件，VHDL硬件描述语言为输入工具，接口简单，可靠性高，具有一定的实用价值。
The programmable logic device and VHDL is used as input tools, which have simple software interface, good reliability and practical value.
该设计采用可编程逻辑器件，ABEL HDL硬件描述语言为输入工具，接口简单，可靠性高，具有一定的实用价值。
The programmable logic device and ABEL-HDL is used as input tools, which have simple software interface, good reliability and practical value.
本系统采用了以DSP、MCU（微控制器）、CPLD（复杂可编程逻辑器件）为核心的系统硬件结构以及数字视频技术。
The system uses DSP, MCU (Microcontrol Unit) and CPLD (Complex Programable Logic Device) as the core of the system hardware and uses digital video technology.
利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
同时大规模可编程逻辑器件飞速发展，为红外图像的实时处理提供了硬件基础。
Meanwhile, the development of large-scale programmable logic device provide a hardware - based for the real time image processing.
利用先进的EDA工具，基于硬件描述语言，借助CPLD（复杂的可编程逻辑器件），可以进行系统级数字逻辑电路的设计。
We can design all kinds of digital logical circuits with advanced EDA tools and based on VHDL and CPLD.
文中采用数据采样插补算法进行粗插补，使用大规模可编程逻辑器件CPLD实现了硬件精插补计算。
The paper discussed a new realization method that rough interpolation is realized by sampled-data interpolation algorithm, and fine interpolation can be gained by CPLD electronic device.
介绍了新型通信控制器的硬件设计，着重描述了通信接口部分，用复杂可编程逻辑器件CPLD解决了CAN 控制器芯片SJA 1000与AT 91RM 9200之间的时序逻辑问题。
The hardware structure is introduced, emphatically the communication interface circuit. The time sequence logic problem between CAN controller chip SJA1000 and AT91RM9200 is solved using the CPLD.
PLC是可编程逻辑电路，也是一种和硬件结合很紧密的语言，在半导体方面有很重要的应用，可以说有半导体的地方就有PLC。
PLC is a programmable logic circuits, and hardware is also a very strong combination of language, in the semiconductor has a very important application, is a place where there semiconductor PLC.
介绍利用复杂可编程逻辑器件CPLD和直接数字合成专用电路dds，设计雷达信号回波模拟器的硬件系统。
Introduce how to design hardware system structure of radar signal echo simulator by using CPLD and DDS.
本文提出了用MCS-51单片机设计简易型可编程序逻辑控制器（PLC）硬件和软件的基本方法。
The basic method of designing a PLC using MCS 51 micro controller is presented in this paper.
本文介绍了一种特殊的硬件实现方法，使用了管脚少、成本低、容易得到的逻辑接口器件，例如可编程逻辑阵列（PAL）、可编程逻辑电路（CPLD）或者FPGA。
The article introduces a unique hardware realization, which utilizes less-foot, low-cost and easy-to-get logistic interfaces, as PAL, CPLD or FPGA.
基于工控机平台，利用CAN总线，PCI-1712数字采集卡和PCL-724可编程逻辑控制器开发了用于检测GD-2ECU硬件可靠性的检测系统。
This paper introduces a reliability diagnosis system specially for GD-2ECU on platform of industrial computer with the help of the CAN card, ADVANTECH's PCI-1712 card and PCL-724 card.
基于工控机平台，利用CAN总线，PCI-1712数字采集卡和PCL-724可编程逻辑控制器开发了用于检测GD-2ECU硬件可靠性的检测系统。
This paper introduces a reliability diagnosis system specially for GD-2ECU on platform of industrial computer with the help of the CAN card, ADVANTECH's PCI-1712 card and PCL-724 card.
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