同时，其鉴频鉴相算法表达式简单，易于用可编程数字器件实现。
The frequency and phase detection module is very easy to realize by programmable digital devices.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
针对检测数字图像灰度梯度的最大值法，采用SOBEL边缘检测算子对数字图像进行边缘检测，并利用硬件(大规模可编程逻辑器件CPLD)实现了数字图像的边缘提取。
The article will contrapose maximum value method based on detecting image grey grad, and take example of SOBEL operator to realize digital image fringe picking up based on hardware (CPLD).
介绍了LED大屏幕扫描电路的设计方法，阐述了可编程逻辑器件在高速数字系统应用中的优点。
The design method of LED big screen scanning circuit is introduced, and the virtues of programmable logic device application on high-speed digital system are presented.
设计了一种交流电机控制系统用于水处理过程控制，采用数字信号处理器TMS320LF 2407配合复杂可编程器件EPM 7256e构成主控系统，并对驱动模块进行设计。
The digital signal processor (DSP) TMS320LF2407 and the complex programmable logic device (CPLD) EPM7256E are used as the main control system and the drive module is also designed.
根据现有的软硬件技术条件，结合实际需要，本论文提出并详细分析了一种新的基于高密度可编程逻辑器件的高动态全数字解扩接收机系统。
On conditions of the current technology, the thesis puts forward a new high dynamic and whole digital spread spectrum receiver which is based on the high density programmable logic devices.
用数字信号处理器(dsp)和复杂可编程逻辑器件(CPLD)设计了IGBT感应加热电源控制系统。
The control system of IGBT induction heating power supply is designed based on DSP (digital signal processor) and CPLD (complex programmable logic device).
介绍了一种应用直接数字频率综合器（DDS）技术，基于可编程逻辑器件（CPLD）和单片机设计的低频信号源。
According to the technology of direct digital synthesis(DDS), a kind of low frequence signal source was introduced based on the Complex Programmed Logical Device(CPLD)and Single Chip Micyoco(SCM).
其控制主体采用DSP（数字信号处理器）结合CPLD（复杂可编程逻辑器件）。
The control mainframe of the robot is composed of a Digital Signal Processor(DSP) and a Complex Programmable Logic Device(CPLD).
本系统采用了以DSP、MCU（微控制器）、CPLD（复杂可编程逻辑器件）为核心的系统硬件结构以及数字视频技术。
The system uses DSP, MCU (Microcontrol Unit) and CPLD (Complex Programable Logic Device) as the core of the system hardware and uses digital video technology.
介绍了一种利用模拟可编程器件和数字可编程器件设计三工位开关控制器的方案，并给出了具体的电路图和程序代码。
A scheme for designing the three-position switch with both analog and digital devices is presented with specific diagram and program code.
可编程逻辑器件FPGA和CPLD正越来越多地替代ASIC和DSP器件，被用于实现数字信号处理算法。
The programmable logical component's FPGA and CPLD substitute ASICand DSP increasingly and are being used to realize the digital signal processing algorithm.
本文分析了可编程逻辑器件出现竞争冒险的原因，介绍了在数字系统设计过程中常用的几种消除竞争冒险的措施。
This paper analyzes the reason for competition risk in PLD and many kinds of methods to avoid competition risk in digital system design are introduced.
现场可编程逻辑器件FPGA以一种新的数字细分技术为原理对计数脉冲做辨向和计数。
FPGA is designed to take count of the counting pulses and distinguish the direction by using a brand new digital subdivision technology.
复杂可编程逻辑器件(CPLD)是目前应用最为广泛的可编程专用集成电路(ASIC)之一，特别适合于数字系统的设计和开发。
Complex Programmable Logic Device (CPLD) is one of Application Specific Integrated Circuit (ASIC) that has been widely used, especially adapt to design digital system.
传统的数字系统通过设计线路板实现系统性能，而可编程器件是通过设计芯片内部的互联逻辑来实现系统功能。
The programmable digital devices implement the logical function by designed internal logic array block while the traditional digital systems do it by designed printed circuit block.
测试系统中采用了以数字信号处理器为核心，以复杂可编程逻辑器件为外围电路，来控制执行部件和测试与接收由外部返回的数字信号、模拟信号和开关信号。
Testing system, in which DSP is the part of core and CPLD is as peripheral circuit, controls operation parts, and test or incept the digital signal, analog signals and switch signals from exterior.
频率通过用可编程器件EPLD控制，而脉冲信号的宽度和幅度通过多路模拟开关和数字电位器调节。
The pulse frequency can be selected by EPLD. The voltage amplitude and pulse width of analog pulse can be adjusted by analog switches and digitally controlled potentiometers.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
在电子技术设计领域，可编程逻辑器件(PLD)的应用为数字系统的设计带来极大的灵活性。
In the field of electronic design, the application of ProgrammableLogic Device (PLD) brought us much convenience.
介绍多媒体公共广播系统的组成及CPLD(可编程逻辑器件)在数字系统设计中的应用，用AHDL语言描述程序设计。
This paper introduces the structure of a multimedia public broadcast system and the application of CPLD in designing a digital system, and gives a description of the program design in AHDL.
数字电路中的竞争冒险是数字系统设计时必须考虑的因素，在可编程逻辑器件中，这一问题变得更加重要。
The competitive risk of digital circuit is an element that should be considered when designing a digital system.
介绍一种针对正、余弦旋转变压器数字转换器（RDC）模块，用复杂可编程逻辑器件（CPLD）技术实现伺服轴角编码电路设计的方案。
This paper introduces the technology scheme to design radar servo shaft encoder circuit by using CPLD on the rotary transformer and RDC module.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
In addition, the device offers programmable decimation rates, and the digital FIR filter can be adjusted if the default characteristics are not appropriate for the application.
利用先进的EDA工具，基于硬件描述语言，借助CPLD（复杂的可编程逻辑器件），可以进行系统级数字逻辑电路的设计。
We can design all kinds of digital logical circuits with advanced EDA tools and based on VHDL and CPLD.
介绍了基于多个DSP芯片- ADSP2 10 60和大规模可编程器件的雷达数字信号处理通用模块。
The universal radar digital signal processing module based on multi DSP ADSP21060 and large scale programmable device is presented.
结论采用复杂可编程逻辑器件替代通用数字集成器件，可提高系统的高频率特性，并提高信号源的信噪比。
So, complex programmable logic device can improve the system's high-frequency performance and signal to noise ratio.
根据单元级联多电平变换器拓扑结构及其脉宽调制技术的特点，以数字信号处理器和复杂可编程逻辑器件为核心，设计了多电平变换器的控制器。
On the basis of topology of cascaded multilevel convertor and its PWM technique, designed the controller of multilevel convertor at the core of DSP and CPLD.
根据单元级联多电平变换器拓扑结构及其脉宽调制技术的特点，以数字信号处理器和复杂可编程逻辑器件为核心，设计了多电平变换器的控制器。
On the basis of topology of cascaded multilevel convertor and its PWM technique, designed the controller of multilevel convertor at the core of DSP and CPLD.
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