在本文的最后部分，使用EDA工具，对一个嵌入式单片机核进行了实际的可测性设计，并对设计结果进行了检查、分析。
In the ending part of this paper, this thesis used EDA tools to accomplish the DFT design task of an embedded MCU core, checked and analyzed the design results.
从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计。
The design of chip test controller of a security chip and design for test of corresponding cores are discussed in detail.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
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