介绍了SOC设计中的IP核可复用技术、软硬件协同设计技术、SOC验证技术、可测性设计技术以及低功耗设计技术。
The paper introduced the technology of IP Reuse, hardware and software co-design, SOC verification, measurement and low-power design on the SOC design.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
介绍了综合软件、硬件、计算机体系结构、超大规模集成技术和可测性的设计方法。
The structured design of integrating software, hardware, computer architecture, VLSI technology and testability together, is introduced.
基于IEEE 1149.1标准的边界扫描技术(BST)作为一种标准化的可测性设计方法，弥补了传统测试的缺陷，为复杂的电路互连提供了测试手段。
As a standard DFT method, IEEE 1149.1 boundary-scan technique (BST) provides measures to complex interconnect test and can well make up the shortcoming of traditional test techniques.
通过对可测性的研究，结合COM技术封装实现了基于多信号建模的可测性辅助设计及分析软件的分配及分析模块。
Based on the research of distribution and anticipation, distribution and analysis functions of DFT-aided design and analysis software combined with com technology are achieved.
本文在对目前主要的可测性设计方法进行研究的基础上，根据所设计CPU的结构特点，采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。
Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test.
实际应用中，大多数器件没有边界扫描接口，因此本文所介绍的边界扫描技术实现方法对进行数字系统的可测性设计具有一定的参考价值。
Meanwhile, how to control the boundary scan bus is mentioned in this paper. As in usual, most devices have no JTAG test access ports, the techniques discussed in this paper are valu…
实际应用中，大多数器件没有边界扫描接口，因此本文所介绍的边界扫描技术实现方法对进行数字系统的可测性设计具有一定的参考价值。
Meanwhile, how to control the boundary scan bus is mentioned in this paper. As in usual, most devices have no JTAG test access ports, the techniques discussed in this paper are valu…
应用推荐