通过可测性设计，使该电路的测试难度及测试时间减少了将近一半。
By design for testability, both the degree of difficulty in testing and test time are reduced nearly one half.
本设计的可测性设计共增加电路面积约4%，端口增加了11 个。
内建自测试作为一种新的可测性设计方法，能显著提高电路的可测性。
As a new method of design for testability build-in self-test can prominently improve the testability of the circuits.
可测性设计的本质就是使电路容易测试，它根本上也要求测试时间的减少。
The essence of DFT is to make the electric circuits test easily, it also requests to decrease the test time basically.
实现了支持积分同时读出(IWR)的相关双采样(CDS)及其可测性设计。
The ROIC can support CDS with IWR (Integration while read) and give the testable design.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
在可测性设计的过程中，把测试功耗和测试时间考虑进去，即为本课题研究的主要内容。
Considering the test power consumption and test time in the process of DFT is the content that this topic mainly studies.
本文介绍了正向设计的局用万门程控交换机专用集成电路CSC71018的可测性设计。
Design for testability of CSC71018, an application-specific IC for programmable switchboard with top-down design, is introduced in the paper.
介绍了A SIC芯片设计时存储器的可测性设计方法，以及存储器对布局布线策略的影响。
The design for testability of memory in ASIC design is dealt with and the influence of memory on placement and routing in IC design is analyzed.
从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计。
The design of chip test controller of a security chip and design for test of corresponding cores are discussed in detail.
在本文的最后部分，使用EDA工具，对一个嵌入式单片机核进行了实际的可测性设计，并对设计结果进行了检查、分析。
In the ending part of this paper, this thesis used EDA tools to accomplish the DFT design task of an embedded MCU core, checked and analyzed the design results.
介绍了SOC设计中的IP核可复用技术、软硬件协同设计技术、SOC验证技术、可测性设计技术以及低功耗设计技术。
The paper introduced the technology of IP Reuse, hardware and software co-design, SOC verification, measurement and low-power design on the SOC design.
全扫描设计通过提升电路的可控制性和可观察性，大大降低了测试生成的复杂度，被认为是最有效的可测性设计方法之一。
Full-scan design which upgrades the circuit in the controllability and observability greatly reduces the complexity of test generation, which is considered the most effective method of DFT.
实际应用中，大多数器件没有边界扫描接口，因此本文所介绍的边界扫描技术实现方法对进行数字系统的可测性设计具有一定的参考价值。
Meanwhile, how to control the boundary scan bus is mentioned in this paper. As in usual, most devices have no JTAG test access ports, the techniques discussed in this paper are valu…
本文以usb逻辑分析仪作为一种典型的被测对象，进行了可测性设计的再开发工作，使其具有支持IEEE 1149.1边界扫描功能的设备结构。
This paper chooses USB logic analyzer as a typical tested object, and carries through a second develop to design it supporting IEEE 1149.1 boundary-scan function for testability.
将以上研究思想应用于国家自然科学基金项目“软件可测性设计新概念—软件内建自测试”，实践证明，该模型有助于软件自动化测试的进一步研究。
Then it comes up with an arithmetic that will be used in regression testing according to the MRD model. This idea has been applied to the project "built-in self test for software…"
基于IEEE 1149.1标准的边界扫描技术(BST)作为一种标准化的可测性设计方法，弥补了传统测试的缺陷，为复杂的电路互连提供了测试手段。
As a standard DFT method, IEEE 1149.1 boundary-scan technique (BST) provides measures to complex interconnect test and can well make up the shortcoming of traditional test techniques.
本文在对目前主要的可测性设计方法进行研究的基础上，根据所设计CPU的结构特点，采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。
Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
而对于数模混合芯片等的测试验证，很大一部分工作还是要依赖于昂贵的仪器来完成，或使用大量的集成电路工程师来进行相关模拟芯片的可测性设计，这样既增加了成本和难度。
A large part of the test and validation for digital-analog hybrid chips is to rely on expensive equipment to carry out or design for test through a large number of IC engineers associated to analog.
通常，用于可测性的设计可以将对象的API推向一种更清晰更模块化的状态。
Often, designing for testability can push the object's API toward a cleaner, more modular state.
MVC设计模式是把应用程序的不同部分分开，来实现更多的伸缩性，扩展性和可测性。
MVC design pattern is used to separate the different parts of the application for more scalability, extensibility and testability purposes.
介绍了综合软件、硬件、计算机体系结构、超大规模集成技术和可测性的设计方法。
The structured design of integrating software, hardware, computer architecture, VLSI technology and testability together, is introduced.
系统设计完善后，需要检验其可测性是否达到设计要求。
Then analyzing the testability of the designed system makes sure whether the design requirements are achieved.
参考模型的选取只与系统的相对阶次有关，而与系统阶次无关，从而简化了控制器的设计，降低了对系统可测性的要求。
The choice of the reference model only depends on the relative degree of the plant but not the degree. The controller design is simplified and the system measurability is less required.
通过对可测性的研究，结合COM技术封装实现了基于多信号建模的可测性辅助设计及分析软件的分配及分析模块。
Based on the research of distribution and anticipation, distribution and analysis functions of DFT-aided design and analysis software combined with com technology are achieved.
通过对可测性的研究，结合COM技术封装实现了基于多信号建模的可测性辅助设计及分析软件的分配及分析模块。
Based on the research of distribution and anticipation, distribution and analysis functions of DFT-aided design and analysis software combined with com technology are achieved.
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