通过改变线性反馈移位寄存器的结构滤掉无效的测试矢量从而实现低功耗测试。
For low power consumption during test mode, the proposed approach ignores the non detecting vectors by altering the structure of LFSR.
本文提出了一种基于受控线性反馈移位寄存器（LFSR）进行内建自测试的结构及其测试矢量生成方法。
A new BIST structure with the method of test vector generation based on a controlled LFSR is proposed.
初步的实验结果表明，从8至24级的线性反馈移位寄存器都可以由1至7级的线性反馈移位寄存器链接构成。
Results from initial experiments show that an 8 ~ 24 degree LFSR can be formed by linking 1 ~ 7 degree LFSR's.
这些多项式是从原始多项式导出的，该原始多项式定义了能够生成伪随机数的线性反馈移位寄存器的反馈函数。
The polynomials are derived from an original polynomial, which defines a feedback function of a linear feedback shift register capable for generating the pseudo random number.
接着，针对生成矩阵的准循环特性，提出了一种新的基于反馈移位寄存器的编码电路，并用FPGA进行了实现。
Next, according to the characteristics of quasi-cyclic matrix, a new encoding circuit using feedback shift registers is proposed and implemented by FPGA.
采用反馈移位寄存器与逻辑门设计了三个典型的编码器电路：基于SRAA电路的串行准循环LDPC码编码器；
Three encoder circuit are designed respectively with feed shift-registers and logic gates: SRAA-based serial QC-LDPC encoder;
对于所有的实验电路，通过使用级数为确定性测试向量的确定位数量最大值的线性反馈移位寄存器，本策略可以编码所有的确定性测试向量。
For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.
本文介绍了一种使用非最长周期序列的非定长线性反馈移位寄存器作为数字系统内部测试生成器的方案，并给出了设计这种测试生成器的设计过程和算法。
In this paper, a scheme is presented, in which an infinite length's LFSR with non maximum cycle sequence is used as a built-in test generator in digital systems.
本文介绍了一种使用非最长周期序列的非定长线性反馈移位寄存器作为数字系统内部测试生成器的方案，并给出了设计这种测试生成器的设计过程和算法。
In this paper, a scheme is presented, in which an infinite length's LFSR with non maximum cycle sequence is used as a built-in test generator in digital systems.
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