右击指定变频器或脉冲反相器。
右击指定变频器或脉冲反相器。
与漏极开路输出的六反相器。
表示常规变换器。可指定变频器或脉冲反相器。
Represents a general changer. Frequency changer or pulse inverter can be specified.
提出了一种不同阈值电压反相器控制的传输门组合结构。
A combinational structure of the transmission gate in the inverter control with different threshold voltages is presented.
该比较器包含一级预放大器、动态锁存器及时钟控制反相器。
The comparator includes a preamplifier, a dynamic latch and a clocked inverter.
反相器2对反相器1进行反相，并提供灵敏放大器电路输出的带负载能力。
The inverter (2) inverts the inverter (1) and provides the carrying load ability for the output of the sensitive amplifier circuit.
储存单元、电流检测器、施密特缓冲器、反相器1、反相器2依次相连接。
The storage unit, the current detector, the Schmidt buffer, the inverter (1) and the inverter (2) are connected in sequence.
每个延迟路径可具有任何合适数目的反相器或任何合适数目的其它类型延迟电路。
Each of the delay paths can have any suitable number of inverters or any suitable number of another type of delay circuit.
如此，在容限电压法当中，直流电压和和有功功率分别被整流器和反相器所控制。
Thus, in the voltage margin method, the dc voltage and the active power are separately controlled by the rectifier and the inverter, respectively.
只有一个输入的数字电路单元是缓冲器或反相器，而输入在一个以上的则称为逻辑门。
Only one input of the digital circuit unit is the buffer or inverter, the input in more than one are called logic gates.
反相器响应低通滤波器的大于或者小于阈值电平的输出，输出处于高或低电平的信号。
An inverter responses the output of a level greater than or smaller than a threshold value of the low pass filter, and outputs a signal in a high level or a low level.
一种二端口SRAM存储器单元(20)包括耦合到存储节点的一对交叉耦合的反相器(40)。
A two-port SRAM memory cell (20) includes a pair of cross-coupled inverters (40) coupled to storage nodes.
电路使用IC4的CD4069反相器作为复位延时使能，在每个计数器开始计数前引入几毫秒的延时。
The circuit uses IC4, a CD4069 inverter, as a reset-delay enable to cause a few milliseconds of delay before each counter can begin to count.
用于包含四个(恒等)电路单元的电子器件或电路的一种术语(“四元组反相器”、“四元组放大器”)。
A term applied to an electronic device or circuit that contains four (identical) circuit units; (" a quad inverter "; "a quad amplifier").
该文以双反相器闩锁电路为基本存贮单元，采用开关级设计方法设计出一种新型的CMOSJK触发器。
Taking the latch composed of two inverters as basic storage unit, this paper proposes a novel CMOS JK flip-flop based on the design at switch level.
从而使TTL反相器和CMOS反相器的电压传输特性曲线能够在示波器荧光屏上形象而又直观地显示出来。
Therefore, the curve of voltage transmission characteristics of both TTL inverter and CMOSinverter can be displayed on the screen of an oscilloscope intuitively.
VIN的上升和下降沿通过反相器501- 504的时间要比通过反相器505 - 506的时间要多。
Rising and falling edges on VIN take more time to travel through inverters 501-504 than through inverters 505-506.
反相器(145、146)将该冲击检出信号(S22、S23)与阈值进行比较，当超过阈值时就是检出冲击。
Inverters (145), (146) compare these impact detecting signals (S22), (S23) with a threshold value and detect an impact when the signals exceeds the threshold value.
同时，为了防止闩锁效应的产生，在电路的大尺寸数字输出反相器的PMOS管和NMOS管的周围增加了保护环。
At the same time, to prevent the generation of latch-up, guard rings are added around the large dimension digital output inverter PMOS and NMOS transistors of the circuits.
该选择信号通过反相器501- 504选择第一延迟路径或通过反相器505 - 506选择第二延迟路径。
The select signal selects the first delay path through inverters 501-504 or the second delay path through inverters 505-506.
本文采用较全面的包括四个寄生双极晶体管和MOS管的闩锁模型，详细分析了瞬态辐照下CMOS反相器的闩锁效应。
In this paper, a new lumped elements latchup model consisting of four bipolar transistors is used to analyze the latchup effect of CMOS inverters in transient radiation environment.
在写入操作结尾，写入字线被去断言，允许交叉耦合的反相器(40)正常工作并且保持存储节点(SN)的逻辑状态。
At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters (40) to function normally and hold the logic state of the storage node (SN).
当选择信号为逻辑高电平（1）时，乘法器510传输反相器504的输出信号给发生器404的输出作为输出信号VOUT。
When the select signal is a logic high (1), multiplexer 510 transmits the output signal of inverter 504 to the output of generator 404 as output signal VOUT.
第五章设计了全p沟道tft构成的屏上驱动电路，包括反相器、移位寄存器、传输门的设计，并用仿真软件进行了仿真验证。
In chapter 5, the on-screen driving circuits composed of P-channel TFT have been designed, including inverter, shift register, transmission gate and simulated using simulation software.
作为另一个示例，当提供给反相器501- 506的电源电压增加时，VIN边缘通过反相器501 - 506的时间减小。
As another example, when the power supply voltage provided to inverters 501-506 increases, the time it takes for edges in VIN to pass through inverters 501-506 decreases.
提出一种采用双谐振器敏感结构的谐振式传感器，传感器的敏感元件包括两个结构参数一致的谐振器，传感器的闭环控制系统由两个幅度控制器和一个反相器组成。
A new resonant sensor consisting of two resonators of uniform structure and size is presented. The closed loop control system is composed of two amplitude controllers and an inverter.
提出一种采用双谐振器敏感结构的谐振式传感器，传感器的敏感元件包括两个结构参数一致的谐振器，传感器的闭环控制系统由两个幅度控制器和一个反相器组成。
A new resonant sensor consisting of two resonators of uniform structure and size is presented. The closed loop control system is composed of two amplitude controllers and an inverter.
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