文章还介绍了该双边沿触发器在时序电路中的应用。
The application of this type of double-edge-triggered flip-flop in seq…
双边沿触发计数器由偶数、奇数加法计数器及数据选择器组成。
Double Edge Trigger counter is composed of odd counter, even counter and data selector.
设计了双边沿触发计数器，并利用电路的冗余特性，降低了系统的功耗。
A double edge triggered counter is designed, and the redundancy attribute of the circuit is utilized to decrease the power consumption of the system.
数据选择器则将两个计数器中处于保持状态的奇偶数据交替输出，实现双边沿触发加法计数器的功能。
Data selector alternately to realize the functions of double edge trigger addition counter output the odd and even data in two counters.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
作为常规ECL门的补充类型，常可用于简化一般ECL电路结构，例如ECL双边沿D触发器。
The ECL OR-AND-gate can simplify a generalized ECL circuits structures, for example, an ECL double-edge-triggered D flip-flop.
作为常规ECL门的补充类型，常可用于简化一般ECL电路结构，例如ECL双边沿D触发器。
The ECL OR-AND-gate can simplify a generalized ECL circuits structures, for example, an ECL double-edge-triggered D flip-flop.
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