这些平台共同工作以表征、建模和分析变化的参数成品率和性能的影响。
These platforms work together to characterize, model and analyze the impact of variability on parametric yield and performance.
集成电路参数成品率的研究是集成电路可制造性工程和设计研究的重要内容之一。
The integrated circuits parametric yield is important problem of the IC designing and manufacture engineering.
超大规模集成电路(VLSI)中的参数成品率最优化问题一直是集成电路可制造性设计的重点研究问题。
The maximum problem of parametric yield in VLSI is always an important issue in design for manufacturing (DFM).
超大规模集成电路(VLSI)中的参数成品率最优化问题一直是集成电路可制造性设计的重点研究问题。
The maximum problem of parametric yield in VLSI is always an important issue in design for manufacturing (DFM).
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