高速数字串行加法器及其应用。
该加法器可以实现两输入的光学算术运算。
This adder can realize the optical arithmetic operation with two inputs.
提出了一种改进进位运算的32位稀疏树加法器。
A 32-bit sparse tree adder with modified carry tree structure is proposed.
所述信 号调制方法包括利用加法器生成和信号的步骤。
The signal modulation method includes generating an added signal with the adder.
所用的方法是，将相加两数的各位同步地输入到加法器中。
The concept used is that the bits of the two numbers to be added are made available to the adder synchronously.
优化方块分配的进位跳跃加法器可以缩短关键路径的延时。
The carry skip adder optimal block sizes can minimize critical path delay.
实验结果表明流水线加法器的速度高于其它结构实现的加法器。
The result of experiment indicates that the pipeline adder is faster others.
提出了一种新的获得二级进位跳跃加法器优化方块分配的算法。
A new type of optimal block distribution algorithm of two level carry-skip adder was described to determine optimal block distribution sizes.
一个简单的加法器描述，以前在别的网站上被发过，现在存在这里。
A simple adder described previously in other websites have been made, and now exist here.
并与功耗、面积约束一起，归纳出超前进位加法器的优化设计规则。
The optimal design rule of CLA was inducted from power dissipation and area constraint, reflect.
该“产生式规则”简单而易以实现，而且不增加浮点加法器的延迟。
The product rule is very simple and easy to implement, and it doesn't increase additional delay.
结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。
It shows that mirrored adder is better than carry look ahead adder in arithmetic speed and layout.
该加法器用于将该第一电功率与该第二电功率相加以得到一第三电功率。
The adder adds the first electric power with the second electric power to gain a third electric power.
根据供给它的控制信号，或起加法器作用或起减法器作用的一种逻辑元件。
A logic element designed to act as either an adder or a subtracter in accordance with the control signal applied to it.
加法器(250)将图像的像素值与反馈计算部分(240)的输出相加。
The adder (250) adds a pixel value of the image and the output of the feedback computing section (240).
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder , which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
该位串行加法器系统是选择了一个由于齿轮数齿轮系统的正常需要，使时钟的计算。
The bit serial adder system was chosen over a normal gear system because of the number of gears it takes to make the clock's calculations.
着重研究了整数加法器、移位器、先导零预测逻辑等浮点加法器关键部件的优化设计。
Integer adder, shifter and LZA these key parts are mainly studied and optimally designed.
浮点加法器是构成CPU的基本部件之一，其性能优劣将直接影响CPU浮点处理能力。
Floating-point adder is one of the basic parts of CPU. Its performance has a direct effect on CPU floating-point processing capacity.
最后在末级加法器阶段，生成器能根据到达的时延不同自动选择不同加法器最优的分段。
Finally the generator can automatically select the best partition point for different types of adders according to various of input delays in the final adder stage.
数字加法器需要更多的电路、因而需要更大的功率才能工作，但它不需要这么高的准确性。
A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.
复数加法运算复杂，用硬件实现复数加法，需要使用数目众多的加法器，占用大量的面积。
Operation of plurality add is very complicated. In the design will numerous adders be used and large area will be consumed.
电子计算机是由具有各种逻辑功能的逻辑部件组成的，加法器就属于其中的组合逻辑电路。
A computer is comprised of some logic parts which have serial logic functions, and the adder is one of the combine logic circuits.
在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。
We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.
反馈计算部分(240)将量化误差进行滤波，并且将滤波结果输出到加法器(250)。
The feedback computing section (240) filters the quantization error and outputs the result of the filtering to the adder (250).
该方案的系统组成包括PC机软件、LXI接口电路、控制模块、多通道dds系统和加法器。
This system could include the PC software, LXI interface circuit, control module, multi-channel DDS system, and the Adder module.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
使用二进制表示法，在每个26位串行加法器动产位的杠杆转换成一个钟摆在摆动的时钟可见符号。
Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.
使用二进制表示法，在每个26位串行加法器动产位的杠杆转换成一个钟摆在摆动的时钟可见符号。
Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.
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