并通过CPU和刷新地址电路共享存储器的方法，对系统输出的校验信号的波形进行编程。
Hz. The waveform of the correcting signal outputted from the system is coded with CPU and address modification circuits sharing the same memory.
其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
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