其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
刷新周期一般由一个叫DRAM控制器的外设完成。
The refresh cycles are usually performed by a peripheral called a DRAM controller.
该视频控制器的以赫兹表示的最大刷新速率。
刷新周期一般由一个叫DRAM控制器的外设完成。
Thee refresh cycles are usually performed by a peripheral called a DRAM controller.
并在FPGA中实现了一个简化的SDRAM控制器，用以完成对SDRAM的初始化、定时刷新、连续读写等功能。
We design a simple SDRAM controller in FPGA to interface with SDRAM, its main tasks are initialization, periodic refreshing, continuous reading and writing.
在将内部复位信号加到CPU的同时，提高由DRAM控制器所生成的用于刷新DRAM中数据的刷新信号的速率。
While the internal reset signal is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller for refreshing data in DRAM is increased.
在将内部复位信号加到CPU的同时，提高由DRAM控制器所生成的用于刷新DRAM中数据的刷新信号的速率。
While the internal reset signal is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller for refreshing data in DRAM is increased.
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