介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。

The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.

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该抢答器单元电路的软件设计分别利用原理图设计、硬件描述语言设计完成。

The circuit software was designed using schematic diagram and hardware description language (VHDL) respectively.

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利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。

Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.

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本文利用VHDL硬件描述语言设计了一种SVPWM信号发生器，该信号发生器不仅成功实现了输入时间信号到SVPWM触发信号的转换，而且具有良好的抗干扰能力。

In this paper, a SVPWM signal generator is designed with VHDL. This signal generator can transform time signal into SVPWM trigger signal successfully with good anti-jamming capability.

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利用先进的EDA工具，基于硬件描述语言，借助CPLD（复杂的可编程逻辑器件），可以进行系统级数字逻辑电路的设计。

We can design all kinds of digital logical circuits with advanced EDA tools and based on VHDL and CPLD.

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本文主要通过FPGA器件，利用HDL硬件描述语言，初步完成了USB设备控制器的设计和实现。

This thesis using FPGA devices and VHDL hardware description language to completed the design and realization of USB equipment controller.

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本文主要通过FPGA器件，利用HDL硬件描述语言，初步完成了USB设备控制器的设计和实现。

This thesis using FPGA devices and VHDL hardware description language to completed the design and realization of USB equipment controller.

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