利用FPGA在硬件上实现了该算法，内部采用流水线技术，校正系数存储在FPGA的片内存储器中并实现了盲元补偿。

In the FPGA design, the pipelined technique is applied and the correction coefficient is stored in the interior memory of FPGA, meanwhile, blind pixel compensation is implemented.

youdao

利用FPGA在硬件上实现了该算法，内部采用流水线技术，校正系数存储在FPGA的片内存储器中并实现了盲元补偿。

In the FPGA design, the pipelined technique is applied and the correction coefficient is stored in the interior memory of FPGA, meanwhile, blind pixel compensation is implemented.

youdao