针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。
This paper presents a high speed test generation method specifically for upper large scale combination circuit (ULSCC) and full scan designed circuit.
在分析全扫描内建自测试(BIST)过高测试功耗原因的基础上，提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗BIST。
Based on the analysis of excessive power dissipation off ull-scan BIST, we present partial scan algorithm which selects a portion of registers for scan cells to implement low power BIST.
建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
全扫描设计通过提升电路的可控制性和可观察性，大大降低了测试生成的复杂度，被认为是最有效的可测性设计方法之一。
Full-scan design which upgrades the circuit in the controllability and observability greatly reduces the complexity of test generation, which is considered the most effective method of DFT.
采用水相悬浮法氯化高全同聚丁烯-1（HIPB-1），其氯化产物氯化高全同聚丁烯-1（CHIPB-1）通过差示扫描量热法进行测试和分析。
High isotactic polybutene-1(HIPB-1)was chlorinated by aqueous suspension method. Chlorination products CHIPB-1 were tested and analyzed through DSC.
全扫描设计中的数据包括测试激励数据以及测试响应所对应的期待响应值。
The design of full-scan data includes test data and the corresponding test response in general, which are stored in the memory of Automatic Test Equipment (ATE).
本文论述了板级边界扫描测试存取口的故障模型和测试原理，并针对全边界扫描印制板提出了一种故障覆盖率高、测试时间短的测试算法。
This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented fort…
本文论述了板级边界扫描测试存取口的故障模型和测试原理，并针对全边界扫描印制板提出了一种故障覆盖率高、测试时间短的测试算法。
This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented fort…
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