为了提高效率，如果由硬件管理虚拟内存，内存是按照所谓的内存页方式进行管理的(对于大部分体系结构来说都是4kb)。
For efficiency, given the way that the hardware manages virtual memory, memory is managed in what are called pages (4kb in size for most architectures).
提高内存，连接和缓冲区的使用，并提供度量的体系。
Improving use of memory, connections and buffers, and to provide metrics.
通过使用压缩，需要从磁盘读入内存的页面更少了，这会提高总体系统性能。
With compression, fewer pages need to be read into memory from disk, making the overall system perform better.
内存结构是IDS体系结构中最为复杂的组件。
Memory structure is the most complicated component of the IDS architecture.
这项更改带来的结果是，固定内存变得更少，并且系统中运行的进程也变得更少；这对于整体系统性能来说，都具有积极影响(请参见清单12)。
As a result of this change, there is less pinned memory and fewer processes that are running on the system; both have positive affects on overall systems performance (see Listing 12).
另外，不同的体系结构具有不同的内存映射支持；共享内存可用的区域也可能不同。
Also, different architectures will have different memory-map support; the areas available for Shared memory could be different.
即便如此，在那些依赖于体系架构的领域、内存映射、线程或一些特殊的领域(例如系统管理和自然语言的支持)，它们之间还是有差异的。
Even so, differences can arise in the areas that depend on the architecture, memory maps, threading, or some specific areas like system administration or natural language support.
每个体系结构子目录都包含了很多其他子目录，每个子目录都关注内核中的一个特定方面，例如引导、内核、内存管理等。
Each architecture subdirectory contains a number of other subdirectories that focus on a particular aspect of the kernel, such as boot, kernel, memory management, and others.
如果有一个64位的DB 2实例，则意味着DB 2使用的是64位的内存体系结构。
If you have a 64-bit DB2 instance, that means DB2 is using the 64-bit memory architecture.
AIX使用内存分段体系结构，以限制共享内存和堆的段的数量。
AIX USES a memory segmented architecture that limits the number of segments used for Shared memory and heap.
注意：本文的后续部分只针对32 位内存体系结构。
Note: The rest of the article will dedicate to 32-bit memory architecture only.
IDS的基本体系结构包括三个主要组件：数据存储器、内存结构和后台处理器或虚拟处理器。
Basic IDS architecture has three major components; data storage, memory structure and background or virtual processors.
现代的处理器在它们的内存模型上有着很大的不同；JMM应该能够适合于实际的尽可能多的体系结构，而不会以牺牲性能为代价。
Modern processors differ substantially in their memory models; the JMM should accommodate as many possible architectures as practical, without sacrificing performance.
在修改后的体系结构中，dumb . c绘制函数将源像素内存区复制到目标内存区。
In the existing architecture we modified, the dumb.c draw function copies the source pixel memory area into the destination memory area.
位体系结构与64位体系结构中的可寻址内存。
Addressable memory in a 32-bit architecture versus 64-bit architecture.
在Windows体系结构中没有真正的内存集概念。
There is no true concept of memory sets on Windows architecture.
本文简要讨论了DB2和Informix的不同方面，例如编辑、体系结构、进程、内存模型、数据库和存储模型。
This article briefly discussed various aspects of DB2 and Informix, such as editions, architecture, process and memory model, databases and storage models.
本文讨论了MySQL和DB 2Express - c备份和恢复机制的许多方面，包括体系结构、内存结构、日志类型以及备份和恢复类型。
This article looked at numerous aspects of both MySQL and DB2 Express-C backup and recovery mechanisms including architecture, memory structure, logging types, and backup and restore type.
对于嵌入式领域，添加了新的体系结构和处理器类型——包括对那些没有硬件控制的内存管理方案的MMU -less系统的支持。
For the embedded world, new architectures and processor types have been added — including support for MMU-less systems that do not have a hardware-controlled memory management scheme.
为了支持根据特定的EPM在Sender与Receiver之间建立连接，Sandesha体系结构将在缺省情况下使用内存中的队列。
In order to support the connectivity between the Sender and the Receiver with respect to a particular EPM, Sandesha architecture USES an in-memory Queue by default.
Itanium体系结构提供的64位寻址去除了32位计算中内存寻址能力上的约束。
The 64-bit addressing provided by the Itanium architecture removes the constraint on memory-addressing capability in 32-bit computing.
另外一种主要的处理器体系结构CISC (x86处理器就是一种流行的CISC指令集)几乎允许在每条指令中进行内存访问。
The other main type of processor architecture, CISC (the x86 processor being a popular CISC instruction set), allows for memory access in nearly every instruction.
介绍了实时操作系统SACOS的特点、体系结构和目标机系统的内存映射。
The features, architecture and target system's memory map of Real-Time Operating System SACOS are introduced.
基于STL代码可重用的小对象内存分配体系由4层结构组成。
The allocation system of small object memory based on STL code consists of 4 layer structures.
本文在简述语音采集压缩卡的硬件体系结构的基础上，重点阐述了驱动程序中多卡管理和内存映射的实现。
This paper design and implement hardware and software of voice record card, and analysis and implement multi -card management and memory map.
在冯。诺依曼体系结构中，没有明确的方法可以区别驻存于内存中的代码和数据。
In the von Neumann architecture there is no definite way to differentiate code and data that is resident in memory.
其中进程控制、内存管理等核心部分与目标机的体系结构密切相关，必须针对目标机单独移植。
The kernel parts of it such as the subsystem process control and memory manager are related with the architecture of target, have to be transplanted alone.
建立了选型模型专家系统的模型功能、框架体系及工作内存。
Model functions, architecture system and working memory have been established.
在当前的体系结构中，如注释中所指出的，你通常最终使用CPU的原子基元和内存子系统提供的一致性协议。
On current architectures, as pointed out in the comments, you mostly end up using the atomic primitives of the CPU and the coherency protocols provided by the memory subsystem.
在当前的体系结构中，如注释中所指出的，你通常最终使用CPU的原子基元和内存子系统提供的一致性协议。
On current architectures, as pointed out in the comments, you mostly end up using the atomic primitives of the CPU and the coherency protocols provided by the memory subsystem.
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