在缓存缺乏一致性的情况下，两个不同的处理器可以看到在内存中同一位置处有两种不同的值。
In the absence of cache coherency, two different processors may see two different values for the same location in memory.
相反，SPU可以以L1缓存的速度来访问本地存储器中的任何128位的字。
Instead, the SPU can access any 128-bit word in the local store at L1 cache speed.
因此，它们并不提供使用 64位JVM保存缓存数据运行应用服务器的替代方案。
As a result, they don't provide an alternative to running an application server with a 64-bit JVM to hold the cached data.
译码单元由指令缓存器和指令译码器构成，针对12位的指令代码翻译成16位控制信号，传送给处理器内部各个部件，用以保证各部件正常工作。
The encoding unit, composed of instruction buffer and command encoder, translates the 12-bit command code to 16-bit control signal, and ensures each part of the system to work steadily.
该电路的设计，应用了数字视频数据信号位面分离的策略，采用了分场写入、分区读出缓存存储器的方法。
The digital video signals bit plane separation strategy is applied in the circuit design, and the sub-field writing-in and sub-area readout to the cache memory method is used.
该电路的设计，应用了数字视频数据信号位面分离的策略，采用了分场写入、分区读出缓存存储器的方法。
The digital video signals bit plane separation strategy is applied in the circuit design, and the sub-field writing-in and sub-area readout to the cache memory method is used.
应用推荐