本论文针对高速互连电路串扰型故障及测试生成方法进行研究。
This paper studies the crosstalk fault and its methods of test pattern generation in high-speed interconnect circuits.
在此基础上运用数值反拉普拉斯变换(nilt)法分析互连电路的时域响应。
Then the numerical inversion of Laplace transform (NILT) is employed for the time domain response of the interconnect circuits.
在一个集成电路中，多个芯片、共享内存以及互连形成了一个紧密集成的多处理核心(参见图4)。
On a single integrated circuit, multiple chips, Shared memory, and an interconnect form a tightly integrated core for multiprocessing (see Figure 4).
因此研究互连延时成为当今进行电路设计和工艺的重点。
Thus, the study of interconnection delay becomes more important for current circuit design and technology.
低温共烧陶瓷(LTCC)技术是实现微波电路与系统小型化、高密度的重要组装和互连技术。
Low temperature co-fired ceramics (LTCC) becomes an important packaging and interconnecting technology for realizing microwave circuit and system's miniaturization and higher density.
SRIO处理器是一个互连技术，并用一个背板使电路板上的芯片相互连接。
A Rapid IO Processor is an inter-connect technology that connects chips on a circuit board and circuit boards to each other using a backplane.
问题可能出在器件的互连或工作在正常的时钟频率时集成电路就不能正常的运行了。
The problem might be an interaction between components or an IC that fails when run at normal operating clock rates.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
总线提供了一种常见的互连系统，它由一组导线或电路组成，在计算机的内部组成部分之间协调和移动信息。
A bus provides a common interconnected system composed of a group of wires or circuitry that coordinates and moves information between the internal parts of a computer.
垂直互连是三维微波和毫米波集成电路中的典型结构。
Vertical interconnections are typical structures in three dimensional microwave and millimeter wave integrated circuits.
设计了红外空间互连旋转连接器的电路。
The circuit of the infrared spatial interconnection rotary joint was designed.
本文首次利用时域有限差分(FDTD)法分析了高速集成电路芯片内半导体基片上的有耗互连传输线的电特性。
A full wave analysis of lossy interconnection lines on doped semiconductor substrates in high speed integrated circuits is carried out by means of a finite difference time domain (FDTD) approach.
本文对应用于超大规模集成电路光学互连的计算机产生的全息图(CGH)的量化及取样影响进行了分析。
The quantization and sampling effects of Computer Generated Hologram (CGH) for optical interconnection of very large scale integrated circuits are dis - cussed.
提出了用来评估深亚微米vlsi电路中rlc互连延时的一种新的解析延时模型。
This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep submicrometer VLSI circuits.
该方法在布线资源中随机产生均匀分布的开路故障，并绕开障碍物布线互连，不依赖于CAD算法和基准电路。
Uniform stochastic open faults are produced in the routing resource, and we route interconnections around obstacles. This method does not depend on CAD tools and benchmark circuits.
利用铜代替铝作为超大规模集成电路的互连接线，代表了半导体工业的重要转变。
Shift from al to Cu interconnects in Ultra-Large Scale Integrate (ULSI) is important for semiconductor industry.
作为VLS I互连线的金属薄膜的截面积越来越小，其承受的功率密度急剧增加，使得电迁移成为电路的主要失效模式之一。
Consequently, the metal interconnects of VLSI have smaller sectional area and carry increasing power density, which made the electromigration become one of the main latent damage modes.
微波电路与低频电路的不同主要在于接地，互连与微带线的制造。
Microwave circuits differ from lower frequency circuits in ground connection, interconnect and manufacturing of the transmission lines.
首先运用全波方法提取互连线的频变等效电路参数。
The frequency dependent parameters of the interconnection lines are extracted by the full wave method firstly.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
第二章论述了现今高速互连设计使用到的分析方法，包括电路方程的表述和模型简化算法。
In Chapter 2, the analysis methods concerned with high speed interconnect design are discussed, including the formulation of circuit equations and model reduction algorithm.
集成电路，一小片内含相互连接的微缩电路的半导体材料。
INTEGRATED circuit, a small piece of semiconductive material that contains interconnected miniaturized electronic circuits.
在大量仿真数据以及当前集成电路设计工艺的基础上，提出了一种简单互连线负载的有效电容计算模型。
A simple and efficient model was presented for computing the effective capacitance of interconnect load based on simulation and integrated circuit process.
论文介绍了互连参数的内容、受集成电路工艺变异的影响及定性方法；
The thesis introduced the interconnect parameters and the influence of process variations and the charactering method.
HPC器件的独特结构减少了由于PC B上的互连线路缩短而引起的寄生现象，并通过缩短组件间的距离提高了电路性能。
HPC devices 'unique construction reduces parasitics by shortening interconnecting traces on PCBs and improves circuit performance by decreasing the distance between components.
它所有的电路元件制成后都接合在一起，而不是用导线分别相互连接。
All of its circuit elements are bonded together rather than separately wired to each other after being manufactured.
分析结果表明，该方法很适合高速集成电路芯片内互连线的计算机辅助分析。
The results show that this method is very fit for the computer aided analysis of on chip interconnects for the high speed VLSI.
并行处理器互连网络的路由算法异常复杂，电路延迟长，逻辑规模巨大，是制约高性能并行处理器提高频率、降低功耗的瓶颈。
The router arithmetic of the parallel processor is complex. The circuit has long latency and the logic has the huge size.
针对高损耗衬底，基于复镜像理论，结合部分元等效电路法，建立了一种新的片上互连线物理模型。
A new physical model for on-chip interconnect on high lossy substrate is proposed based on complex image theory and PEEC.
针对高损耗衬底，基于复镜像理论，结合部分元等效电路法，建立了一种新的片上互连线物理模型。
A new physical model for on-chip interconnect on high lossy substrate is proposed based on complex image theory and PEEC.
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