对互连寄生电容提取的研究背景进行了简要的介绍。
In this paper, the background of parasitic capacitance extraction of interconnects are briefly introduced.
在大量仿真数据以及当前集成电路设计工艺的基础上，提出了一种简单互连线负载的有效电容计算模型。
A simple and efficient model was presented for computing the effective capacitance of interconnect load based on simulation and integrated circuit process.
基于“有效电容”的概念提出了一种分析两相邻耦合r C互连延时的方法。
An approach for analyzing coupling rc interconnect delay based on "effective capacitance" is presented.
在3dVL SI互连寄生电容的边界元素法计算中，多孔平面的边界元划分是十分困难的问题。
In the computations of 3d VLSI parasitic interconnect capacitance, it is very difficult to partition the boundary elements on a multi hole surface.
在充分考虑互连线的电容耦合效应和电感耦合效应的前提下，提出了一种有效估算互连串扰噪声的方法。
This paper presents a new time-efficient method for the estimation of crosstalk, which considers the effect of coupling capacitances and inductors completely.
阐述了超大规模集成电路（ VLSI）特征尺寸的减小及互连线层数增加引起的互连线电容增加的问题。
The issue of interconnect capacitance rising from very large scale integration(VLSI)with a decreased feature size and increased number of wiring layers is described.
介绍复杂互连寄生电容器的结构及对其实现虚拟多介质切割的方法。
In this paper, the complex 3D structures of VLSI interconnect capacitors and the virtual cutting method for them are presented.
我们再也不能如同处理低速设计一般，视互连为集总电容或简单的延迟线。
It is no longer possible to model interconnects as lumped capacitors or simple delay lines, as could be done on slower designs.
我们再也不能如同处理低速设计一般，视互连为集总电容或简单的延迟线。
It is no longer possible to model interconnects as lumped capacitors or simple delay lines, as could be done on slower designs.
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