需要一个串行累减二进制计数器。
它采用二进制计数器以把被乘数由并行形式转换成脉冲序列形式。
It USES binary counters for the conversion of the multiplicand from parallel to pulse-train form.
组合计数器的最大数值是二进制计数器和反馈计数器的级数的函数。
The maximum count of a combination counter is thus a function of the number of stages of the binary and feedback counters .
和普通的二进制计数器相比具有很好的稳定性和可靠性，为计数器的设计提供了参考。
Compared with the ordinary binary counter, it has high stability and flexibility. This method is a reference to design of counter.
这很容易做到，注意，对于二进制计数器，只要所有前面的数字都是1，任何给定的数字都会改变它的值(从1变为0，或者从0变为1)。
This can be easily done by nothing that, for a binary counter, any given digit changes its value (from 1 to 0 or from 0 to 1) whenever all the previous digits have a value of 1.
这个二进制串由常用的计数器(DB 2max函数进行实际聚集计算时需要)、聚集对象的标识以及分组标识构成。
This binary string is comprised of the usual counter, which is needed for the DB2 MAX function to do the actual aggregation, the identifier for the aggregate object, and the group identifier.
该中间结果用二进制形式编码表示，并通过一个经过编码的计数器逐渐增加。
The intermediate result is encoded in a binary representation and appended at the beginning by an encoded counter.
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。
The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
三位二进制加1与加2计数器：三位二进制模5计数器。
The three binary counter plus 1 and plus 2: three binary mod 5 counter.
原始条件：使用D触发器（ 74LS 74 ）、“与”门 （ 74 LS08 ）、“或”门（ 74 LS32 ）、非门 （ 74 LS04 ），设计三位二进制模5计数器。
Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
原始条件：使用D触发器（ 74LS 74 ）、“与”门 （ 74 LS08 ）、“或”门（ 74 LS32 ）、非门 （ 74 LS04 ），设计三位二进制模5计数器。
Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
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