高速数字串行加法器及其应用。
该位串行加法器系统是选择了一个由于齿轮数齿轮系统的正常需要，使时钟的计算。
The bit serial adder system was chosen over a normal gear system because of the number of gears it takes to make the clock's calculations.
使用二进制表示法，在每个26位串行加法器动产位的杠杆转换成一个钟摆在摆动的时钟可见符号。
Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.
下面显示的行星，每个位串行加法器控制，显示的元素，太阳系仪，其中每一个对应计算出地球的轨道。
Below the planetary display, each bit serial adder controls one element of the display, the orrery, each of them corresponding to calculate that planet's orbit.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
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