在用中规模集成逻辑电路实现函数时，使用降维卡诺图可化简多变量函数。
When using MSI to implement logical functions, we can use Reduced-dimension Karnaugh Map (RDM) to simplify multi-variable functions.
介绍了高速中规模集成数字频率合成器、晶体管高频大功率放大器的设计。
The high-speed digital frequency mixer made of medium-scale integrated circuits and the design of a high power transistor amplifier are also presented.
提出了利用中规模集成计数器芯片设计任意位数系列脉冲发生器的方法；并举例说明了应用。
The paper introduces the method of using medium-scale integrated calculator core to design the arbitrary digit sequence pulse generator and gives examples to illustrate its application.
介绍以中规模集成计数器为核心，结合中规模集成组合逻辑器件及少量门电路进行时序逻辑电路设计的方法。
This paper introduces one way to design scheduling logic circuit with medium-scale integrated counter at the core and based on MSI.
本文指出了中规模集成计数器的三个特点，提出带引脚关系描述的逻辑功能表有助于我们对集成计数器的认识建立一个全局的概念。
An overall point view to understand integrated circuit counter is brought forward based on logic function table which reflect the relationships between pins on the integrated circuit.
在工程实践中利用中规模集成电路设计组合逻辑电路需要在设计理念和方法上做一定的改进，以适应工程设计计算机化和工程实际的要求。
It needs to have new ideas and ways in design to use Mid-scale integrate circuit to improve the Combined Logical circuit in engineering to meet the requirements of computerizing engineering design.
集成电路规模的增加，使电路的可测试性成了设计阶段必须考虑的问题，这就需要预先确定电路中各部份的测试性能。
As the scale of IC is increasing, its testability must be taken into account in the course of circuit design and the testability measure of circuits should be determined.
优化设置可以溶入我们的驱动方案中，使得低电压和低电流可以满足大规模集成（VLSI）的要求。
The optimal settings can be incorporated into our driving scheme so that low voltage and current requirements can be met for very large scale integration(VLSI)implementation.
借鉴超大规模集成电路物理设计中的相关思想，提出基于有序树的设施紧置布置编码表示法。
A representation for compact layout of logistics facilities based on an O-tree (ordered tree) was proposed following the approach for design of very large integrated circuit.
它们有一个低功耗与低输出阻抗的简单结构，可以用作超大规模集成电路设计中的接口电路，以减少基片的外部引线数。
They have a simple construction with low power dissipation and low output impedance and can be used as interfacing circuits in VLSI designs to reduce the number of external connections on a chip.
该电路为中规模数模混合集成电路。
The circuit is the medium scale digital and analog mixed integrated circuit.
两层通道布线问题在超大规模集成电路自动布图设计中是关键步骤之一。
Two-layer channel routing is one of the key steps in the automatic layout design of VLSI chips.
该试剂用于清除匀胶后残留于硅片边缘及背面的光刻胶，已经广泛应用于中、大规模集成电路及其它半导体器件的生产。
The chemical is widely used in the production of LSI, VLSI and other semiconductors to remove photoresist edge bead that occurs during typical spin coat wafer processing.
介绍用中规模数字集成电路设计组合逻辑电路的原理和方法。
In this article, the method and theory of designing composite logic circuit by using middle scale digital integrated circuits is discussed.
光刻是大规模集成电路生产流程中十分关键的一环，而光刻中使用的掩模的质量对大规模集成电路的成品率有很大的影响。
In the manufacture process of integrated circuit (IC), lithography occupy a very important step, and the quality of photomask used in lithography affects the yield of LSI.
本文提出了大规模集成电路中互连线的特征模型。
The characteristic model of interconnects in VLSI is proposed.
综述了亚微米、深亚微米干法刻蚀和相关技术的最新进展及其在超大规模集成电路制造中的应用。
The latest advance of the dry etching for submicron fabrication in ULSI production and interrelated technology are introduced.
论文针对目前大规模集成电路设计要求，结合电力电子应用，设计了一个SPWM信号产生系统IP软核，该软核可广泛应用于系统级芯片设计中。
According to the requirement of the VLSI and the wide application of power electronics, IP soft core of SPWM generation system is designed. And it can be widely applied in system level chip design.
在大规模作战仿真系统开发中，可推广使用模型测试平台，提高模型可靠性，降低集成成本，缩短集成周期。
In large-scale combat simulation system development, the promotion of model testing platform can improve the model reliability, reduce the integration costs and shorten the integration period.
互联网上有大量信息隐藏在网络数据库中，其规模庞大且更新速度快，传统数据集成方法不适应集成这些信息。
A lot of information is hidden in database of deep Web. As it has vast volume and grow rapidly, the conventional approach of data integrating is not suitable for integrating it.
超大规模集成电路(VLSI)中的参数成品率最优化问题一直是集成电路可制造性设计的重点研究问题。
The maximum problem of parametric yield in VLSI is always an important issue in design for manufacturing (DFM).
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
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