利用两级敏感放大器的层次式结构，一方面使第一级放大的信号成为真正的数字信号，另一方面增加了电路的驱动能力。
The sense amplifier's hierarchical architecture can be used, not only to make the signals amplified to true digital signals, but also to add the drive of the circuits.
该光接收机采用单电源供电，由一级放大器、两级源级跟随器和一个反馈电阻组成。
It is composed of an amplifier stage, two stages of source follower and a feedback resistance, and use a single supply voltage.
采用位线平衡技术、高速两级敏感放大器及可预置电压的数据输出缓冲，以提高存储器的读写频率。
A fast access time is obtained by utilizing a bit line equalizing technique, a high speed hierarchical sense amplifier and a preset data output buffer.
同时，利用两级敏感放大器的层次式结构降低数据线的电压幅度，进一步降低了功耗。
In addition, the sense amplifier's hierarchical architecture can be used to reduce the data bus voltage amplitude, which further reduces the power dissipation.
核心电路为两级直接耦合差分放大器。
The core circuit is two stages of direct-coupled difference amplifier.
给出了一种常用两级低电压CMOS运算放大器的输入级、中间增益级及输出级的原理电路图，并阐述其主要工作特性。
The principle figures of input stage middle gain stage and output stage for a usual two stage low-voltage CMOS operational amplifier and their principal performance are presented in the paper.
列读出级采用新型主从两级放大列读出结构，其中主放大器完成电荷到电压的转换，从放大器驱动输出总线来满足一定的读出速度。
In the design of column readout stage, master and slaver structure has been adapted, where master amplifier converts charge to voltage, and slave amplifier works with standby mode to drive output bus.
列读出级采用新型主从两级放大列读出结构，其中主放大器完成电荷到电压的转换，从放大器驱动输出总线来满足一定的读出速度。
In the design of column readout stage, master and slaver structure has been adapted, where master amplifier converts charge to voltage, and slave amplifier works wit.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
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