高速数据总线技术是航空电子中的关键技术之一。
High speed data bus technology is one of the core techniques in avionics.
摘要：高速数据总线技术是航空电子中的关键技术之一。
Absrtact: High speed data bus technology is one of the core techniques in avionics.
高速数据总线是先进军机航空电子综合化的关键支撑技术。
High speed data bus is the key technology in avionics integration for advanced fighters.
高速数据总线技术是航空电子综合化最重要的支撑技术之一，直接决定整机航电系统综合化程度的高低。
High speed data bus technology is one of the key technologies in avionics integration, which has direct influence on the performance of the avionics system of tactical aircraft.
视频介绍上的并行lvcmos总线串行数据序列化为一个高速差分信号。
The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal.
本文提出了一种基于I2C总线及其分割技术的串行传输方法，可有效解决高速串行传输系统中的数据延迟问题。
This paper gives a serial transmission method which bases on the I2C BUS and its division. Wehave effectively solved the data delay in high speed serial data transmission system.
PC与DSP的数据交换采用高速静态RAM，并设计总线仲裁电路及相应的握手信号，以保证PC与DSP双方对RAM的正确读写。
PC and DSP exchange data using high speed static RAM and bus arbitration circuit and corresponding handshake signal is designed to ensure the correct reading and writing RAM.
在实际的工作中，把PC I局部总线和SCSI系统总线结合起来，使整个系统拥有高速的数据吞吐量，以期实现图象数据的实时采集和快速存储，为实时处理和事后分析工作提供充分的观测数据。
In fact, in order to realize image data real-time collecting and rapid storage, uniting PCI bus and SCSI bus which make system hold high speed data throughput provides sufficiency observation data.
通过对美国军用标准MIL-STD-1553B总线协议在高速数据通讯中受到限制的分析，提出了现实解决办法。
The research puts forward the methods of solving the problems by analyzing the limitations which MIL-STD-1553 B data bus protocol possesses in high speed data communication.
研究了基于PCI总线的高速数据采集系统的设计方法；
The paper states the design method of high speed data acquiring system based on PCI bus.
给出了一个以CPLD为控制核心的基于计算机PCI总线高速数据采集系统的设计实例。
In the paper, a design example of the high speed data acquisition system based on PCI bus of computer with CPLD as a control kernel is introduced.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
通用串行总线作为一种崭新的微机总线接口规范，其特点使其非常适合高速数据采集系统。
As a new computer bus interface criterion, USB ap-plies to the high-speed data collecting system.
总线控制协议是高速多路串行数据总线的关键，它决定了多路串行数据总线的实时响应能力以及在高负载和低负载情况下的串行数据总线的特性。
Bus control protocol is the key or high rate multiplex data bus. The capacity of real—time responseness of multiplex data bus and properties in high and low load are decided by the protocol.
介绍了一种基于PCI总线的高速数据采集传输系统的实现方法。
A new way to design the data acquisition system based on PCI local bus is realized.
文中着重介绍了工业控制机isa总线及其与高速数据采集卡的接口技术。
The interface between ISA bus and high-speed data sampling card is the emphasis of this paper.
本文从硬件设计和驱动程序开发两个方面对基于PCI总线的高速数据采集卡进行了研究。
PCI bus-based high-speed data acquisition board, including hardware design and driver program, is researched in this paper.
现场总线直接连接现场的工业设备，需要完成生产过程中大量数据的高速采集、处理和传输。
Field-bus connects the industrial equipments in the field, undertake the task of high-speed acquisition, processing and transmission of a large number of data in production.
本文主要对以OF DM技术为核心的高速数据通信总线的若干关键技术和具体实现进行了研究。
In this dissertation, the detail methods of implementing high-speed data bus system which is based on OFDM technique are researched.
本文探讨了一种基于64位PCI总线的高速数据采集与存储系统的设计与实现方法。
This paper discusses the design and implementation methods of a high-speed data acquisition and storage system based on 64-bit PCI bus.
双端口ram是一种特殊的数据存储芯片，利用双端口ram可以实现双高速单片机总线方式的数据共享。
The dual-ported RAM is a kind of special memory, and the bus data share between double high-speed microprocessors is carried out by using it.
目的研究VME计算机总线扩展的仪器标准总线(VXI)超高速数据采集与DSP系统的设计与实现。
Aim To study the design and realization of ultra high speed data acquisition and DSP system based on VME computer bus expended for instruments (VXI) bus.
文章介绍了如何通过PCI局部总线实现高速的数据传送，即介绍了对PC I接口板的开发介绍，其中包括它的硬件协议和软件协议的讨论。
It introduces how to design a PCB board of high speed data transmitting system based on PCI part bus, including the discussing of hardware agreement and software agreement.
该系统以80c552单片机为控制核心，采用总线隔离技术，实现高速数据采集与数据处理分时进行。
This system with the control core of 80c552 single chip processor adopts bus isolation technique, realizing the time-sharing processing of high-speed data collecting and data processing.
提出一种基于TMS320C 6711的具有USB(通用串行总线)接口的高速数据传输的设计方案，对TMS320C 6711和USB处理器an2131 Q的软硬件设计作了详细介绍。
A design scheme of high-speed data transmission with the interface of USB based on TMS320C6711 is presented. And the hardware and software design of TMS320C6711 and AN2131Q are described in detail.
通用串行总线USB已成为PC的标准接口，它可以实现高速的数据传递。
USB has been a PC standard interface which can transfer data in high speed.
介绍了采用CPLD实现DSP芯片TMS320C6713和背板VME总线之间高速数据传输的系统设计方法。
The method of using CPLD to realize high speed datatrasmission between DSP chip TMS320C6713 and VMEbus onthe backboard is described.
CLB总线是一种片上系统总线，一般用来连接高速度、高数据宽度的IP。
The CLB bus is a kind of on-chip system bus which is usually used to connect IPs with high speed and high data width.
CLB总线是一种片上系统总线，一般用来连接高速度、高数据宽度的IP。
The CLB bus is a kind of on-chip system bus which is usually used to connect IPs with high speed and high data width.
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