时钟抖动是输出时钟的随机变化。
延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。
The delay circuit is used for both frequency and phase adjustments of the output clock.
输出时钟抖动定义为三种类型：周期抖动，占空比抖动和相位抖动。
Output jitter is defined in three ways: period jitter. duty-cycle jitter, and phase jitter.
频率比较器比较基准时钟和输出时钟的频率，并输出频率比较信号。
A frequency comparator compares the frequency of a reference clock with that of an output clock and outputs a frequency comparison signal.
相位比较器比较基准时钟和输出时钟的相位，并输出相位比较信号。
A phase comparator compares the phase of the reference clock with that of the output clock and outputs a phase comparison signal.
CPLD电路设计采用图像传感器的输出时钟触发sdram写过程。
The design of CPLD has adopted the output clock of image sensor to write SDRAM.
输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。
The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.
如果对所有组件使用相同的跟踪系统，您将被迫协调系统的多个输出，从而可能面临内部时钟不同步的风险。
If you're using the same trace system for all your components, you'll be left to tie together multiple outputs from systems with potentially unsynchronized internal clocks.
最后，启动myobservable时钟，查看如清单6所示的输出。
Finally, start MyObservable's clock to see output like that in Listing 6.
此输出显示任务的列表（根据任务ID 编号）、其总执行时间（时钟节拍内）、等待执行的时间量以及调用的次数。
This output shows the list of tasks (numbered by task ID), their total execution time (in ticks), the amount of time they waited to execute, and finally the number of times they were invoked.
如果一个标志是要传输时，输出变为高电平后，在时钟的上升沿。
If a mark is to be transmitted, the output goes high after the rising edge of the clock.
关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。
The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
在尽量减少时钟消耗的前提下，此解码器可以解码每个变换块中变换系数的熵编码码流，并将结果按照块扫描顺序并行输出。
While minimizing the use of clock cycles, it could decode the coded stream of transform coefficients in each block and output the decoded coefficients in zigzag scanning order.
触发器以这样的方式相互联接，使一个触发器的输出成为下一个的时钟，依此类推。
The flip-flops are attached to each other in a way so that the output of one acts as the clock for the next, and so on.
在串行数据输入（DI）或输出（DO）时使用的时钟信号。
Used as the synchronization clock when inputting (DI) or outputting (DO)serial data.
在串并转换接收器中，并行数据在字节时钟的作用下并行输出。
In the deserializer, parallel data are clocked out by byte clock.
每个解码输出在一个全时钟周期内保持高电平。
串行口对时方式：装置通过串行口读取同步时钟每秒一次的串行输出的时间信息对时，串行口又分为rs232接口和RS422接口方式。
Mode of serial port pair: synchronous clock device through the serial port read per second pair a serial output time information, serial port and RS232 interface and RS422 interface.
该电度表的控制电路主要由信号检测、实时时钟、输出控制电路及68hc 705c8单片机组成。
The control circuit of the Kilowatt-hour meter consists mainly of the circuit of signal detection, real-time clock and control of output, and it also consists of 68hc705c8 single chip computer.
补偿器包括控制为输出选择哪个写时钟相位的相位旋转器。
The compensator includes a phase rotator that controls which write clock phase is selected for output.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
将所得定时误差输出到写时钟补偿器。
The resulting timing error is output to a write clock compensator.
文中还提出了用偏振全息术获得多输出端时钟分布的方案。
Methods for obtaining multiple fan out clock distribution using polarization holographic technique is also proposed.
可以提供输入及输出用于引入及输出精确参考时钟信号。
Inputs and outputs are provided for bringing in and outputting precision reference clock signals.
论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。
And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.
论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。
And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.
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